28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究

文溢; 陈建军; 梁斌; 池雅庆; 黄俊

doi:10.12263/DZXB.20211691

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28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究

学术论文 | 更新时间：2025-12-08

- 28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究
- Research on Single-Event Radiation Characteristics of an 8-Gbps SerDes in a 28nm CMOS Technology
- 电子学报 2022年50卷第11期页码：2653-2658
- 作者机构：
  
  国防科技大学计算机科学学院，湖南长沙 410073
- 作者简介：
  
  [ "文溢　男，1992年3月生，湖南长沙人.现为国防科技大学计算机学院微电子所工程师.主要从事集成电路设计与抗辐照加固设计等方面的研究工作.E-mail: wenyi19920312@126.com" ]
  [ "陈建军（通讯作者）　男，1983年10月生，贵州毕节人.博士毕业于国防科技大学电子科学与技术专业，现任国防科技大学计算机学院研究生导师，主要研究方向为高速通信系统和集成电路设计的抗辐照加固技术." ]
  [ "梁斌　男，1979年7月生，湖南常德人.博士毕业于国防科技大学电子科学与技术专业，现任国防科技大学计算机学院研究生导师，主要研究方向为高速通信系统和集成电路设计的抗辐照加固技术.E-mail: liangbin110@126.com" ]
  [ "池雅庆　男，1982年2月生，重庆沙坪坝人.博士毕业于国防科技大学电子科学与技术专业，现任国防科技大学计算机学院研究生导师，主要研究方向为高速通信系统和集成电路设计的抗辐照加固技术.E-mail: yqchi@nudt.edu.cn" ]
  [ "黄俊　女，1991年10月生，湖南长沙人.现为国防科技大学计算机学院微电子所工程师.主要从事集成电路设计与抗辐照加固设计等方面的研究工作.E-mail: 654302416@qq.com" ]
- 基金信息：
  
  国家自然科学基金(61974163);国防科技大学高层次创新人才培训计划项目(4142D125106;434517212306)
- DOI：10.12263/DZXB.20211691
  中图分类号： TN402
- 收稿：2021-12-23，
  
  修回：2022-07-09，
  
  纸质出版：2022-11-25
- 稿件说明：
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文溢,陈建军,梁斌等.28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究[J].电子学报,2022,50(11):2653-2658.

WEN Yi,CHEN Jian-jun,LIANG Bin,et al.Research on Single-Event Radiation Characteristics of an 8-Gbps SerDes in a 28nm CMOS Technology[J].ACTA ELECTRONICA SINICA,2022,50(11):2653-2658.
文溢,陈建军,梁斌等.28nm CMOS工艺8-Gbps SerDes单粒子辐射特性研究[J].电子学报,2022,50(11):2653-2658. DOI： 10.12263/DZXB.20211691.

WEN Yi,CHEN Jian-jun,LIANG Bin,et al.Research on Single-Event Radiation Characteristics of an 8-Gbps SerDes in a 28nm CMOS Technology[J].ACTA ELECTRONICA SINICA,2022,50(11):2653-2658. DOI： 10.12263/DZXB.20211691.

摘要

本文研究了28nm体硅CMOS工艺下8-Gbps通用结构高速并转串/串转并接口（Serializer/Deserializer，SerDes）的单粒子辐射特性，该SerDes由电压模发送器（Transmitter，TX）和相位插值（Phase Interpolation，PI）型接收器（Receiver，RX）组成，通过双指数电流源对整个SerDes的TX和RX进行了单粒子效应仿真，仿真结果表明该SerDes的TX和RX均会发生单粒子瞬态（Single-Event Transient，SET），且主要敏感节点包括：D触发器，采样器和时钟相位插值器.进一步采用脉冲激光对整个SerDes进行了扫描测试，测试结果验证了仿真结论.该研究为抗辐射SerDes的研制提供了重要的理论依据.

Abstract

In this paper

single-event radiation characteristics of an 8-Gbps high-speed Serializer/Deserializer interface(SerDes) is studied in a 28nm bulk CMOS technology. The SerDes

which is composed of a voltage mode transmitter(TX) and a phase interpolating(PI) receiver(RX)

is simulated by a double exponential current source to find the sensitive node

and the simulation results show both the TX and RX appear single-event transient(SET) and the main sensitive nodes of the whole SerDes include D flip-flop

samplers and clock phase interpolators. These sensitive nodes are further verified through pulsed-laser single-event experiment

and the study provides an important theoretical basis for the design of radiation-hardened SerDes.

关键词

Keywords

references

ARMSTRONG S E , OLSON B D , POPP J , et al . Single-event transient error characterization of a radiation-hardened by design 90nm SerDes transmitter driver [J]. IEEE Transactions on Nuclear Science , 2009 , 56 ( 6 ): 3463 - 3468 .

ARMSTRONG S E , OLSON B D , HOLMAN W T , et al . Demonstration of a differential layout solution for improved ASET tolerance in CMOS A/MS circuits [J]. IEEE Transactions on Nuclear Science , 2010 , 57 ( 6 ): 3615 - 3619 .

YUAN H Z , CHEN J J , LIANG B , et al . An SEU/SET-tolerant phase frequency detector with double loop self-sampling technology for clock data recovery [J]. IEEE Transactions on Nuclear Science , 2019 , 66 ( 7 ): 1483 - 1490 .

YUAN H Z , CHEN J J , LIANG B , et al . Fault-tolerant multi-node coupling triple mode redundancy voltage controlled oscillator for reducing soft error in clock and data recovery [J]. Electronics Letters , 2019 , 55 ( 5 ): 250 - 251 .

YUAN H Z , GUO Y , CHEN J J , et al . 28 nm fault-tolerant hardening-by-design frequency divider for reducing soft errors in clock and data recovery [J]. IEEE Access , 2019 , 7 : 47955 - 47961 .

ZANCHI Z , BUCHNER S , HAFER C , et al . Investigation and mitigation of analog SET on a bandgap reference in triple-well CMOS using pulsed laser techniques [J]. IEEE Transactions on Nuclear Science , 2011 , 58 ( 6 ): 2570 - 2577 .

ZHAO Q F , YANG G Q , SUN Y J , et al . Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology [J]. Microelectronics Reliability , 2017 , 73 : 116 - 121 .

SAVOJ J , RAZAVI B . A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector [J]. IEEE Journal of Solid-State Circuits , 2001 , 36 ( 5 ): 761 - 768 .

TAN J W , GUO Y , CHEN J J , et al . A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit [C]//CHEN M H. 2017 IEEE 12th International Conference on ASIC . Guiyang : IEEE , 2017 : 339 - 342 .

YUAN H Z , CHEN J J , LIANG B , et al . A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath-current-releasing technology [C]// CHEN M H . Proceedings of International Conference on ASIC, 2017 IEEE 12th International Conference on ASIC . Guiyang : IEEE , 2017 : 241 - 244 .

ZHENG X Q , ZHANG C , LV F X , et al . A 40-Gb/s quarter-rate SerDes transmitter and receiver chipset in 65-nm CMOS [J]. IEEE Journal of Solid-State Circuits , 2017 , 52 ( 11 ): 2963 - 2978 .

IM J , FREITAS D , ROLDAN A B , et al . A 40-to-56 Gb/s PAM-4 receiver with ten-tap direct decision-feedback equalization in 16-nm FinFET [J]. IEEE Journal of Solid-State Circuits , 2017 , 52 ( 12 ): 3486 - 3502 .

HAO P P , CHEN S M , WU Z Y , et al . On-chip relative single-event transient/single-event upset susceptibility test circuit for integrated circuits working in real time [J]. IEEE Transactions on Device and Materials Reliability , 2018 , 65 ( 1 ): 376 - 381 .

GUO S , LI J , GUI P , et al . Single-event transient effect on a self-biased ring-oscillator PLL and an LC PLL fabricated in SOS technology [J]. IEEE Transactions on Nuclear Science , 2013 , 60 ( 6 ): 4668 - 4672 .

HAO P P , CHEN S M . Single-event transient susceptibility analysis and evaluation methodology for clock distribution network in the integrated circuit working in real time [J]. IEEE Transactions on Device and Materials Reliability , 2017 , 17 ( 3 ): 539 - 548 .

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