超低导通电阻沟槽栅LDMOS器件研究
Research on Ultra-Low On-Resistance Trench Gate LDMOS Device
- 电子学报 2023年51卷第8期 页码：1995-2002
- 作者机构：
1.东南大学电子科学与工程学院,江苏南京 210096
2.东南大学微电子学院,江苏无锡 214000
3.无锡华润上华科技有限公司,江苏无锡 214000
- 作者简介：
[ "吝晓楠 男，1998年生.现为东南大学电子科学与工程学院研究生.主要研究方向为功率半导体器件可靠性.E-mail: linxnnj@qq.com" ]
[ "刘斯扬（通讯作者） 男，1987年生.现为东南大学电子科学与工程学院教授、博士生导师.主要研究方向为新型功率器件设计、功率集成电路设计和功率器件建模.中国电子学会会员：E190029952M. Email: liusy2017@seu.edu.cn" ]
- 基金信息：国家重点研发计划(2020YFF0218501);东南大学至善学者基金(2242021R41080)
DOI：10.12263/DZXB.20220020
中图分类号： TN323+.4;收稿：2022-01-03，
修回：2022-06-23，
纸质出版：2023-08-25
- 稿件说明：
移动端阅览
吝晓楠,吴团庄,许超奇等.超低导通电阻沟槽栅LDMOS器件研究[J].电子学报,2023,51(08):1995-2002.
LIN Xiao-nan,WU Tuan-zhuang,XU Chao-qi,et al.Research on Ultra-Low On-Resistance Trench Gate LDMOS Device[J].ACTA ELECTRONICA SINICA,2023,51(08):1995-2002.
吝晓楠,吴团庄,许超奇等.超低导通电阻沟槽栅LDMOS器件研究[J].电子学报,2023,51(08):1995-2002. DOI： 10.12263/DZXB.20220020.
LIN Xiao-nan,WU Tuan-zhuang,XU Chao-qi,et al.Research on Ultra-Low On-Resistance Trench Gate LDMOS Device[J].ACTA ELECTRONICA SINICA,2023,51(08):1995-2002. DOI： 10.12263/DZXB.20220020.
摘要
本文提出了一种具有超低特征导通电阻的沟槽栅横向双扩散场效应晶体管（Trench Gate Lateral Double-diffused MOSFET，TG-LDMOS）.本结构源极和漏极都在表面，与BCD（Bipolar CMOS DMOS）工艺相兼容.通过引入介质沟槽、垂直栅极、栅极下方的源极多晶硅以及栅极右侧的厚氧化层，将传统集成型功率器件的一维耐压拓宽为二维耐压，包括横向耐压与纵向耐压两个方向.其中，纵向耐压不占用横向元胞尺寸，进而在相同耐压水平上，使TG-LDMOS具有分立功率器件耐压效率高、导通电阻低的特点.本结构通过仿真优化做到了击穿电压（
V
B
）为52 V，特征导通电阻（
R
on，sp
）为10 mΩ·mm
2
.结果表明，TG-LDMOS突破了硅器件的极限关系，与硅极限相比特征导通电阻降低了48%.
Abstract
A trench gate lateral double-diffused MOSFET (TG-LDMOS) with ultra-low specific on-resistance (
R
on
sp
) is proposed. With source and drain contact placement at the top silicon surface
our device is compatible with BCD (Bipolar CMOS DMOS) technologies. Compared with conventional integrated power devices
by introducing the dielectric trench
vertical gate
polysilicon source and thick oxide layer
one-dimensional withstand voltage is broadened to two-dimensional withstand voltage
including both lateral and vertical directions. The vertical withstand voltage doesn't occupy the lateral cell pitch
just like the discrete power devices
so that our device has the characteristics of high voltage withstand efficiency and low on-resistance at the same breakdown voltage (
V
B
). The TG-LDMOS is optimized to achieve
V
B
of 52 V and
R
on
sp
of 10 mΩ·mm
2
. The simulation results show that the TG-LDMOS breaks through the silicon limit
and
R
on
sp
is reduced by 48% compared with the silicon limit.
关键词
Keywords
references
HE N L , ZHANG S , ZHU X H , et al . A 0.25μm 700V BCD technology with ultra-low specific on-resistance SJ-LDMOS [C ] // 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) . Piscataway : IEEE , 2020 : 419 - 422 .
姚佳飞 , 郭宇锋 , 李曼 , 等 . 高k介质阶梯变宽度SOI LDMOS [J ] . 电子学报 , 2018 , 46 ( 7 ): 1781 - 1786 .
YAO J F , GUO Y F , LI M , et al . Novel SOI LDMOS with step width drift region using high-k dielectric [J ] . Acta Electronica Sinica , 2018 , 46 ( 7 ): 1781 - 1786 . (in Chinese)
代红丽 , 赵红东 , 王洛欣 , 等 . 具有L型栅极场板的双槽双栅绝缘体上硅器件新结构 [J ] . 电子学报 , 2018 , 46 ( 5 ): 1146 - 1152 .
DAI H L , ZHAO H D , WANG L X , et al . A dual-trench-gate silicon on insulator device with a L-shaped gate field plate [J ] . Acta Electronica Sinica , 2018 , 46 ( 5 ): 1146 - 1152 . (in Chinese)
MEHRAD M . Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors [J ] . Materials Science in Semiconductor Processing , 2015 , 30 : 599 - 604 .
WU L J , ZHANG W T , SHI Q , et al . Trench SOI LDMOS with vertical field plate [J ] . Electronics Letters , 2014 , 50 ( 25 ): 1982 - 1984 .
PUNETHA M , SINGH Y . Dual-channel trench LDMOS on SOI for RF power amplifier applications [J ] . Journal of Computational Electronics , 2016 , 15 ( 2 ): 639 - 645 .
PAYAL M , SINGH Y . A multi-channel trench-gate radio frequency LDMOS on silicon-on-insulator [J ] . IETE Technical Review , 2017 , 34 ( 3 ): 246 - 253 .
MEHROTRA S , RADIC L , GROTE B , et al . Towards ultimate scaling of LDMOS with Ultralow Specific On-resistance [C ] // 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) . Piscataway : IEEE , 2020 : 42 - 45 .
YUAN , WANG , . Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers [J ] . Results in Physics , 2020 , 19 : 103589 .
WU L J , HUANG Y , WU Y Q , et al . Investigation of the stepped split protection gate L-Trench SOI LDMOS with ultra-low specific on-resistance by simulation [J ] . Materials Science in Semiconductor Processing , 2019 , 101 : 272 - 278 .
YUAN N , WU L J , YANG H , et al . Double trenches LDMOS with trapezoidal gate [J ] . Micro & Nano Letters , 2018 , 13 ( 5 ): 695 - 698 .
KOJIMA J Y , MATSUDA J I , KAMIYAMA M , et al . Optimization and analysis of high reliability 30–50V dual RESURF LDMOS [C ] // 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) . Piscataway : IEEE , 2017 : 392 - 394 .
JIN F , LIU D H , XING J J , et al . Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology [C ] // 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) . Piscataway : IEEE , 2017 : 295 - 298 .
WANG Y D , DUAN B X , YANG Y T . Experimental of folded accumulation lateral double-diffused transistor with low specific on resistance [C ] // 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) . Piscataway : IEEE , 2021 : 195 - 198 .
KAUSHAL K N , MOHAPATRA N R . A zero-cost technique to improve ON-state performance and reliability of power LDMOS transistors [J ] . IEEE Journal of the Electron Devices Society , 2021 , 9 : 334 - 341 .
LI M Z , DUAN B X , YANG Y T . New strained silicon-on-insulator lateral MOSFET with ultralow ON-resistance by Si 1- x Gex P-top layer and trench gate [J ] . IEEE Electron Device Letters , 2021 , 42 ( 6 ): 788 - 791 .
WEI Y X , LUO X R , GE W W , et al . A split triple-gate power LDMOS with improved static-state and switching performance [J ] . IEEE Transactions on Electron Devices , 2019 , 66 ( 6 ): 2669 - 2674 .
LUO X R , MA D , TAN Q , et al . A split gate power FINFET with improved ON-resistance and switching performance [J ] . IEEE Electron Device Letters , 2016 , 37 ( 9 ): 1185 - 1188 .
LUO X R , LV M S , YIN C , et al . Ultralow ON-resistance SOI LDMOS with three separated gates and high- k dielectric [J ] . IEEE Transactions on Electron Devices , 2016 , 63 ( 9 ): 3804 - 3807 .
GUO S N , HUANG H M , CHEN X B . Study of the SOI LDMOS with low conduction loss and less gate charge [J ] . IEEE Transactions on Electron Devices , 2018 , 65 ( 4 ): 1645 - 1649 .
WU L J , YUAN N , LEI B , et al . Split-gate LDMOS with double vertical field plates [J ] . Micro & Nano Letters , 2018 , 13 ( 11 ): 1580 - 1584 .
0
浏览量
26
下载量
1
CSCD
- 网络PDF下载
- Meta-XML下载
- BibTeX下载
- Endnote下载
- RefMan 下载
- NoteExpress下载
- NoteFirst下载
关联资源
相关文章
相关作者
相关机构
- 技术支持由北京北大方正电子有限公司提供 京ICP备09064830号-19
京公网安备11010802024621 - 本系统建议在Chrome、 IE9+ 以上版本浏览器阅读本站内容，360浏览器请切换至极速模式
- Cookies帮助我们提供服务并提供个性化体验。使用本网站，即表示您同意我们使用Cookies