面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法

郭仲杰; 许睿明; 程新齐; 余宁梅; 苏昌勖; 李晨

doi:10.12263/DZXB.20220022

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面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法

学术论文 | 更新时间：2025-12-08

- 面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法
- High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors
- 电子学报 2023年51卷第8期页码：2067-2075
- 作者机构：
  
  西安理工大学自动化与信息工程学院，陕西西安 710048
- 作者简介：
  
  [ "郭仲杰男，1982年出生，陕西韩城人.教授.主要研究方向为超大规模数模混合集成电路的设计.E-mail: zjguo@xaut.edu.cn" ]
  [ "许睿明男，1997年出生，内蒙古人.西安理工大学自动化与信息工程学院硕士研究生.主要研究方向为超大规模集成电路设计.E-mail: 1170253565@qq.com" ]
- 基金信息：
  
  国家自然科学基金(62171367);陕西省重点研发计划(2021GY-060);陕西省创新能力支撑计划(2022TD-39)
- DOI：10.12263/DZXB.20220022
  中图分类号： TN47;
- 收稿：2022-01-03，
  
  修回：2022-03-29，
  
  纸质出版：2023-08-25
- 稿件说明：
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郭仲杰,许睿明,程新齐等.面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法[J].电子学报,2023,51(08):2067-2075.

GUO Zhong-jie,XU Rui-ming,CHEN Xin-qi,et al.High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors[J].ACTA ELECTRONICA SINICA,2023,51(08):2067-2075.
郭仲杰,许睿明,程新齐等.面向亿级CMOS图像传感器的高速全并行两步式ADC设计方法[J].电子学报,2023,51(08):2067-2075. DOI： 10.12263/DZXB.20220022.

GUO Zhong-jie,XU Rui-ming,CHEN Xin-qi,et al.High Speed Fully Parallel Two-Step ADC Design Method for Hundred Million Level CMOS Image Sensors[J].ACTA ELECTRONICA SINICA,2023,51(08):2067-2075. DOI： 10.12263/DZXB.20220022.

摘要

针对传统单斜式模数转换器（Analogue-to-Digital Conversion，ADC）和串行两步式ADC在面向大面阵CMOS图像传感器读出过程中的速度瓶颈问题，本文提出了一种用于高速CMOS图像传感器的全并行两步式ADC设计方法，该ADC设计方法基于时间共享和时间压缩思想，将细量化时间提前到粗量化时间段内，解决了传统方法的时间冗余问题；同时针对两步式结构在采样过程中的电荷注入和时钟馈通问题，提出了一种基于误差同步存储技术的误差校正方法，消除了采样电路非理想因素对ADC性能的影响.本文基于55 nm 1P4M CMOS工艺对所提方法完成了详细电路设计和全面测试验证，在模拟电压为3.3 V，数字电压为1.2 V，时钟频率为250 MHz，输入信号为1.472 V的设计条件下，本文设计实现的13 bit ADC转换时间为512 ns，DNL（Differential NonLinearity）为

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19.21933365

2.28600001

，INL（Integral NonLinearity）为

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19.55800056

2.28600001

.信噪失真比（Signal to Noise and Distortion Ratio，SNDR）达到70 dB，有效位数为11.33 bit，列级功耗为47 μW.相比现有的先进ADC，本文提出的方法在保证低功耗、高精度的同时，使ADC转换速率提高了74.4%以上，为高速高精度CMOS图像传感器的读出与量化提供了一定的理论支撑.

Abstract

Aiming at the speed bottleneck problem of traditional single-slope analog-to-digital converter (ADC) and serial two-step ADC in the readout process of large-array CMOS image sensors

this paper proposes a fully parallel two-step ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression

advances the fine conversion time to the coarse conversion time period

and solves the time redundancy problem of the traditional method. At the same time

aiming at the Charge Injection and Clock Feedthrough problems in the sampling process of the two-step structure

an error correction method based on the error synchronization storage technology is proposed

which eliminates the impact of the non-ideal factors of the sampling circuit on the performance of the ADC. Based on the 55 nm 1P4M CMOS process

this paper has completed the detailed circuit design and comprehensive test verification of the proposed method. Under the design conditions of analog voltage 3.3 V

digital voltage 1.2 V

clock frequency 250 MHz and input signal 1.472 V

the proposed 13-bit ADC achieves the differential nonlinearity (DNL) of +0.8/-0.8LSB and the integral nonlinearity (INL) of +2.1/-3.5LSB and Conversion time of 512 ns .The effective number of bits (ENOB) is 11.33 bit and the power consumption is 47 μW. Compared with the existing advanced ADCs

the method proposed in this paper can increase the ADC conversion rate by more than 74.4% while ensuring low power consumption and high precision

providing certain theoretical support for the readout and conversion of high-speed and high-precision CMOS image sensors.

关键词

Keywords

references

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