MRNDA：一种基于资源受限片上网络的深度神经网络加速器组播机制研究

欧阳一鸣; 王奇; 汤飞扬; 周武; 李建华

doi:10.12263/DZXB.20220106

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MRNDA：一种基于资源受限片上网络的深度神经网络加速器组播机制研究

学术论文 | 更新时间：2025-12-11

- MRNDA：一种基于资源受限片上网络的深度神经网络加速器组播机制研究
- MRNDA: A Multicast Mechanism for Resource-Constrained Noc-Based Deep Neural Network Accelerators
- 电子学报 2024年52卷第3期页码：872-884
- 作者机构：
  
  1.合肥工业大学计算机与信息学院，安徽合肥 230009
  2.合肥工业大学微电子学院，安徽合肥 230009
- 作者简介：
  
  [ "欧阳一鸣男，1963年出生，安徽合肥人.合肥工业大学计算机与信息学院教授、博导，中国计算机学会高级会员.主要研究方向为片上网络（NoC）与片上系统（SoC）、嵌入式系统的综合与测试、数字系统设计自动化. E-mail: oyym@hfut.edu.cn" ]
  [ "王奇男，1994年出生，安徽滁州人.2016年于吉林大学获学士学位，2018年于美国斯蒂文斯理工学院获硕士学院.合肥工业大学微电子学院博士生.主要研究方向为片上网络容错设计、智能片上网络、神经网络加速器设计. E-mail: keywenchester@outlook.com" ]
- 基金信息：
  
  国家自然科学基金(61874157;71971151)
- DOI：10.12263/DZXB.20220106
  中图分类号： TP302;
- 收稿：2022-01-21，
  
  修回：2022-07-15，
  
  纸质出版：2024-03-25
- 稿件说明：
移动端阅览
欧阳一鸣,王奇,汤飞扬,等.MRNDA：一种基于资源受限片上网络的深度神经网络加速器组播机制研究[J].电子学报,2024,52(03):872-884.

OUYANG Yi-ming, WANG Qi, TANG Fei-yang, et al.MRNDA: A Multicast Mechanism for Resource-Constrained Noc-Based Deep Neural Network Accelerators[J].Acta Electronica Sinica, 2024, 52(03): 872-884.
欧阳一鸣,王奇,汤飞扬,等.MRNDA：一种基于资源受限片上网络的深度神经网络加速器组播机制研究[J].电子学报,2024,52(03):872-884. DOI：10.12263/DZXB.20220106

OUYANG Yi-ming, WANG Qi, TANG Fei-yang, et al.MRNDA: A Multicast Mechanism for Resource-Constrained Noc-Based Deep Neural Network Accelerators[J].Acta Electronica Sinica, 2024, 52(03): 872-884. DOI：10.12263/DZXB.20220106

摘要

片上网络（Network-on-Chip，NoC）在多处理器系统中得到了广泛的应用.近年来，有研究提出了基于NoC的深度神经网络（Deep Neural Network，DNN）加速器.基于NoC的DNN加速器设计利用NoC连接神经元计算设备，能够极大地减少加速器对片外存储的访问从而减少加速器的分类延迟和功耗.但是，若采用传统的单播NoC，大量的一对多数据包会极大的提高加速器的通信延迟.并且，目前的深度神经网络规模往往非常庞大，而NoC的核心数量是有限的.因此，文中提出了一种针对资源受限的NoC的组播方案.该方案利用有限数量的处理单元（Processor Element，PE）来计算大型的DNN，并且利用特殊的树形组播加速网络来减少加速器的通信延迟.仿真结果表明，和基准情况相比，本文提出的组播机制使加速器的分类延迟最高降低了86.7%，通信延迟最高降低了88.8%，而它的路由器面积和功耗仅占基准路由器的9.5%和10.3%.

Abstract

Network-on-Chip (NoC) devices have been widely used in multiprocessor systems. In recent years

NoC-based deep neural network (DNN) accelerators have been proposed to connect neural computing devices using NoCs. Such designs dramatically reduce off-chip memory accesses of these platforms thus reduce the accelerators’ classification latency and power consumption. However

the large number of one-to-many packet transfers significantly increase the communication latency with traditional unicast channels. We proposed a multicast mechanism for resource-constrained noc-based deep neural network accelerators (MRNDA) to compute large DNN models by using limited number of processor elements (PEs). This paper proposes a tree-based multicast acceleration network to decrease the communication latency of DNN accelerators. Simulation results show that

compared with the baseline method

the multicast mechanism proposed in this paper reduces the classification latency of the accelerator by up to 86.7% and the communication latency by up to 88.8%

while its router’s area and power only account for 9.5% and 10.3% of the baseline routers.

关键词

Keywords

references

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