基于IEEE 802.1AS的多跳时钟同步算法与系统实现
Multi-Hop Clock Synchronization Algorithm and System Implementation Based on IEEE 802.1AS
- 电子学报 2024年52卷第3期 页码：814-823
- 作者机构：
重庆邮电大学通信与信息工程学院，重庆 400065
- 作者简介：
[ "赵国锋 男，1972年11月出生于陕西省西安市.现为重庆邮电大学通信与信息工程学院教授、博士生导师.主要研究方向为工业互联网、天地一体化网络和网络测量.E-mail: zhaofg@cqupt.edu.cn" ]
[ "危瑞鹏 男，1999年5月出生于江西省抚州市.现为重庆邮电大学通信与信息工程学院硕士研究生.主要研究方向为时间敏感网络高精度同步协议开发.E-mail: 965223383@qq.com" ]
[ "邢 媛 女，1992年6月出生于山西省运城市.现为重庆邮电大学通信与信息工程学院博士研究生.主要研究方向为时间敏感网络确定性调度模型和算法.E-mail: xingystudy@foxmail.com" ]
[ "徐 川 男，1980年12月出生于重庆市.现为重庆邮电大学通信与信息工程学院教授、博士生导师.主要研究方向为未来网络、工业互联网、天地一体化网络和网络测量.中国电子学会会员编号：E190025974M.E-mail: xuchuan@cqupt.edu.cn" ]
[ "张汝凤 女，1999年1月出生于四川省雅安市.现为重庆邮电大学通信与信息工程学院硕士研究生.主要研究方向为时间敏感网络同步协议和调度协议.E-mail: 1464253025@qq.com" ]
- 基金信息：国家自然科学基金(62171070);国家重点研发计划项目(2018YFB1800301;2018YFB1800304);重庆市研究生科研创新项目(CYB19176);重庆邮电大学博士研究生人才培养项目(BYJS201905)
DOI：10.12263/DZXB.20220304
中图分类号： TP393收稿：2022-03-24，
修回：2022-10-26，
纸质出版：2024-03-25
- 稿件说明：
移动端阅览
赵国锋,危瑞鹏,邢媛,等.基于IEEE 802.1AS的多跳时钟同步算法与系统实现[J].电子学报,2024,52(03):814-823.
ZHAO Guo-feng, WEI Rui-peng, XING Yuan, et al.Multi-Hop Clock Synchronization Algorithm and System Implementation Based on IEEE 802.1AS[J].Acta Electronica Sinica, 2024, 52(03): 814-823.
赵国锋,危瑞鹏,邢媛,等.基于IEEE 802.1AS的多跳时钟同步算法与系统实现[J].电子学报,2024,52(03):814-823. DOI：10.12263/DZXB.20220304
ZHAO Guo-feng, WEI Rui-peng, XING Yuan, et al.Multi-Hop Clock Synchronization Algorithm and System Implementation Based on IEEE 802.1AS[J].Acta Electronica Sinica, 2024, 52(03): 814-823. DOI：10.12263/DZXB.20220304
摘要
针对现有IEEE 802.1AS协议中单一主时钟无法保障多跳网络下高精度同步的问题，提出一种基于多属性决策的冗余时钟同步方法.首先，基于链路拥塞程度、节点拓扑属性和时钟源质量系数对时钟属性值进行建模；其次，采用多属性决策算法选取最佳主时钟并生成冗余时钟序列表；最后，利用FPGA（Field Programmable Gate Array）平台设计并实现冗余时钟同步系统，同时搭建真实网络环境对所提方法进行测试.结果表明，相较于现有方法，时钟同步精度提升了68%，主时钟失效后重新同步所需收敛时间减小了60%.
Abstract
Aiming at the problem that a single master clock in the existing IEEE 802.1AS protocol cannot guarantee the high precision of clock synchronization in multi-hop network
a redundant clock synchronization method based on multi-attribute decision-making is proposed. Firstly
the clock attribute value is modeled based on the link congestion degree
topology attribute of node and clock source quality factor. Secondly
the multi-attribute decision-making algorithm is used to select the best master clock and generate a redundant clock sequence table; Finally
the redundant clock synchronization system is designed and implemented on field programmable gate array (FPGA) platform
and a real network environment is constructed to test the proposed method. The results show that
compared with the existing methods
the clock synchronization accuracy is improved by 68%
and the convergence time required for resynchronization after master clock failure is reduced by 60%.
关键词
Keywords
references
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