基于量子元胞自动机的
n 位全加器设计Design of
n -bit Full Adder Based on Quantum-Dot Cellular Automata- 电子学报 2024年52卷第2期 页码：626-632
- 作者机构：
合肥工业大学微电子学院，安徽合肥 230009
- 作者简介：
[ "张辉 男，1996年02月出生，安徽亳州人.硕士研究生.主要研究方向为QCA电路的优化设计. E-mail: 3291144827@qq.com" ]
[ "解光军 男，1970年08月出生，安徽合肥人.教授，博士.主要研究方向为纳米器件与电路、集成电路设计. E-mail: gjxie8005@hfut.edu.cn" ]
[ "张永强 男，1991年03月出生，安徽阜阳人.讲师，博士.主要研究方向为集成电路设计、非精确计算. E-mail: ahzhangyq@hfut.edu.cn" ]
- 基金信息：中央高校基本科研业务费专项资金资助(JZ2020HGTA0085);青年教师科研创新启动专项(JZ2020HGQA0162)
DOI：10.12263/DZXB.20220324
中图分类号： TN4;收稿：2022-03-29，
修回：2023-03-13，
纸质出版：2024-02-25
- 稿件说明：
移动端阅览
张辉,解光军,张永强. 基于量子元胞自动机的n位全加器设计[J]. 电子学报,2024,52(02):626-632.
ZHANG Hui, XIE Guang-jun, ZHANG Yong-qiang. Design of n-bit Full Adder Based on Quantum-Dot Cellular Automata[J]. Acta Electronica Sinica, 2024, 52(02): 626-632.
张辉,解光军,张永强. 基于量子元胞自动机的n位全加器设计[J]. 电子学报,2024,52(02):626-632. DOI：10.12263/DZXB.20220324
ZHANG Hui, XIE Guang-jun, ZHANG Yong-qiang. Design of n-bit Full Adder Based on Quantum-Dot Cellular Automata[J]. Acta Electronica Sinica, 2024, 52(02): 626-632. DOI：10.12263/DZXB.20220324
摘要
量子元胞自动机（Quantum-dot Cellular Automata，QCA）以其功耗低、纳米级设计、运算速度高等特点被认为是一门新兴技术，在不久的将来有望取代CMOS工艺，用于量子计算机的电路设计.近年来，在QCA电路中有很多使用三输入择多门（
M
3
）和三输入异或门（XOR
3
）设计的全加器（Full Adder，FA）.本文以这两种逻辑门为基础，结合QCA电路特有的时钟特点，设计了三种新型的
n
位全加器（FA1，FA2，FA3）.FA1只使用了一个1位全加器，它的元胞的数量和电路面积比已发表的8位全加器至少减少了78%和90%，但一个时钟周期只能完成1位计算，延迟较大；FA2的元胞的数量和电路面积比已发表的8位全加器至少减少了47%和63%，可以在一个时钟周期内完成2位计算；FA3在一个时钟周期内可以进行4位计算，延迟最小.FA1、FA2和FA3作为
n
位全加器，随着全加器位数的增加，它们的元胞的数量和电路面积是不会改变的，这是以往设计所不能实现的.
Abstract
Quantum-dot cellular automata (QCA) is considered as an emerging technology
because of its unique characteristics such as low power consumption
nanoscale design
and high computing speed
which can be used as an alternative for CMOS technology in circuit design for quantum computers in the near future. In recent years
many FAs (Full Adder) are designed using three-input majority gate (
M
3
) and three-input XOR gate (XOR
3
) in QCA circuits. Three new types of
n
-bit full adders (FA1
FA2 and FA3) are designed based on these two logic gates and the unique clock characteristics of QCA circuits in this paper. FA1 is implemented using only a 1-bit FA
and its cell number and circuit area are reduced by at least 78% and 90% by comparing with the published 8-bit FA. But FA1 can only calculate one bit in one clock cycle
so it has a large delay. The number of cells and circuit area of FA2 are reduced by at least 47% and 63% by comparing with the published 8-bit full adder. And FA2 can calculate two bits in one clock cycle. FA3 can perform four-bit calculations in one clock cycle with minimum delay. As
n
-bit full adders
the number of cells and circuit area of FA1
FA2 and FA3 will not change with the increase of the number
n
which can’t be realized by the previous design.
关键词
Keywords
references
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