工艺-电压-温度综合稳健的亚1 V 10位SAR ADC

张畅; 佟星元

doi:10.12263/DZXB.20221017

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工艺-电压-温度综合稳健的亚1 V 10位SAR ADC

学术论文 | 更新时间：2025-12-08

- 工艺-电压-温度综合稳健的亚1 V 10位SAR ADC
- A Sub-1 V 10 bit SAR ADC Robust Against Process-Voltage-Temperature Variation
- 电子学报 2023年51卷第8期页码：2050-2057
- 作者机构：
  
  西安邮电大学陕西省通信专用集成电路设计工程技术研究中心，陕西西安 710121
- 作者简介：
  
  [ "张畅男，1999年生，河北廊坊人.西安邮电大学电子工程学院硕士研究生.主要研究方向为数模混合信号集成电路设计.E-mail: zhangchangzc_z@163.com" ]
  [ "佟星元（通讯作者）男，1984年生.博士，博士后.西安邮电大学教授、陕西省通信专用集成电路设计工程技术研究中心主任.主要研究方向为低功耗集成电路设计、数据转换器电路、传感电路与系统. Email: mayxt@126.com" ]
- 基金信息：
  
  国家自然科学基金(62271389);陕西省高层次人才特殊支持计划(2018TZBJ-36);陕西省教育厅重点科学研究计划(22JY058)
- DOI：10.12263/DZXB.20221017
  中图分类号： TN432;
- 收稿：2022-09-02，
  
  修回：2023-02-16，
  
  纸质出版：2023-08-25
- 稿件说明：
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张畅,佟星元.工艺-电压-温度综合稳健的亚1 V 10位SAR ADC[J].电子学报,2023,51(08):2050-2057.

ZHANG Chang,TONG Xing-yuan.A Sub-1 V 10 bit SAR ADC Robust Against Process-Voltage-Temperature Variation[J].ACTA ELECTRONICA SINICA,2023,51(08):2050-2057.
张畅,佟星元.工艺-电压-温度综合稳健的亚1 V 10位SAR ADC[J].电子学报,2023,51(08):2050-2057. DOI： 10.12263/DZXB.20221017.

ZHANG Chang,TONG Xing-yuan.A Sub-1 V 10 bit SAR ADC Robust Against Process-Voltage-Temperature Variation[J].ACTA ELECTRONICA SINICA,2023,51(08):2050-2057. DOI： 10.12263/DZXB.20221017.

摘要

采用0.11-µm CMOS工艺设计了一款10位亚1 V工艺-电压-温度（Process-Voltage-Temperature，PVT）综合稳健的逐次逼近寄存器型（Successive-Approximation-Register，SAR）模数转换器（Analog-to-Digital Converter，ADC）IP核.由于SAR ADC数字化程度较高，为了降低整体功耗，采用小于标准电压的亚1 V供电.然而，对于异步SAR ADC，在低压下面临严峻的PVT不稳健问题，传统采用固定延迟电路的方式无法应对所有的PVT偏差，会导致ADC良率下降.提出一种用于异步SAR ADC的可配置延迟调控技术，采用3输入译码器调节延迟电路的电流，以满足ADC在多种PVT组合下所需的延时，在TT，SS，FF，SF，FS这5种工艺角，0.9~1 V供电范围和-40~85 ℃的温度范围下，均取得了良好的动态特性.在0.95 V供电，采样速率为200 kS/s时，总功耗为2.24 μW，FoM值仅为16.46 fJ/Conv.-step.

Abstract

A 10 bit successive-approximation-register (SAR) analog-to-digital converter (ADC) is designed by using 0.11

https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=61161373&type=

https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=61161364&type=

1.69333339

2.96333337

m CMOS technology. It can operate with sub-1 V supply voltage and is robust against process

voltage

and temperature (PVT) variation. Since SAR ADC is with a highly digitized structure

a sub-1 V power supply which is smaller than the standard supply voltage is used for power reduction. However

asynchronous SAR ADCs are sensitive to PVT fluctuations

especially under low supply voltages. The commonly used delay circuit in asynchronous SAR ADC usually features fixed delay without any configurable function

so that the ADC cannot operate properly under all PVT conditions

leading to the degradation of ADC yield. A programmable delay-controlling technique is proposed in this paper for asynchronous SAR ADC. A 3-to-8 line decoder is used to control the adjustment of current supplied to the delay circuit

so that different delay requirements of the ADC under different PVT conditions can be satisfied. The post-layout simulation results verify its robustness against variations of process corners (TT

SF and FS)

supply voltage from 0.9 V to 1 V

and temperature from -40 ℃ to 85 ℃. With a supply voltage of 0.95 V and a sampling rate of 200 kS/s

the power consumption of this ADC is 2.24 μW

and the FoM value is only 16.46 fJ/Conv.-step.

关键词

Keywords

references

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ZHU Z M , QIU Z , LIU M L , et al . A 6-to-10-bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 μm CMOS [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2015 , 62 ( 3 ): 689 - 696 .

ZHANG C C , JIN Z R , LIU D S . A 1.1-V 10-bit 25-MS/s 7.58fJ/conversion-step SAR ADC in 40-nm CMOS [C ] // 2021 9th International Symposium on Next Generation Electronics (ISNE) . Piscataway : IEEE , 2021 : 1 - 4 .

ZHANG D , BHIDE A , ALVANDPOUR A . A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices [C ] // 2011 Proceedings of the ESSCIRC (ESSCIRC) . Piscataway : IEEE , 2011 : 467 - 470 .

ZHANG H S , ZHANG H , SONG Y , et al . A 10-bit 200-KS/s 1.76 <math id="M3"><mi mathvariant="normal">μ</mi><mi mathvariant="normal">W</mi></math> https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=61161697&type= https://html.publish.founderss.cn/rc-pub/api/common/picture?pictureId=61161694&type= 4.74133301 2.96333337 SAR ADC with hybrid CAP-MOS DAC for energy-limited applications [J ] . IEEE Transactions on Circuits and Systems I: Regular Papers , 2019 , 66 ( 5 ): 1716 - 1727 .

WANG S J , DEHOLLAIN C . Design and implementation of a rail-to-rail 460-kS/s 10-bit SAR ADC for the power-efficient capacitance measurement [J ] . IEEE Transactions on Instrumentation and Measurement , 2015 , 64 ( 4 ): 888 - 901 .

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