1.大数据技术与系统国家地方联合工程研究中心/服务计算与系统教育部重点实验室/集群与网格计算湖北省重点实验室, 华中科技大学,湖北武汉 430074
2.华中科技大学计算机科学与技术学院,湖北武汉 430074
[ "靳晓忠 男,1997年出生于内蒙古呼和浩特.2019年获得华北电力大学学士学位.目前正在华中科技大学攻读博士学位,研究兴趣主要包括数据去重和存储系统.E-mail: xzjin@hust.edu.cn" ]
[ "刘海坤 男,1981年出生于湖北随州.华中科技大学教授,博士生导师,国家级人才入选.2012年于华中科技大学计算机系统结构专业博士毕业,目前主要从事内存型存储系统、异构计算、机器学习等方向的研究.先后主持多项国家自科基金项目、国家重点研发计划课题以及10多项企业横向合作项目.E-mail: hkliu@hust.edu.cn" ]
[ "赖 皓 男,1997 年出生于广东韶关 .2021年获华中科技大学计算机科学与技术硕士学位,主要研究方向为计算机系统结构、FPGA. E-mail: laihao@bigo.sg" ]
[ "毛伏兵 男,1985出生于湖北仙桃.硕士生导师,2018年获新加坡南洋理工大学计算机科学与工程博士学位.主要研究方向为,系统软件与体系结构、FPGA/AISC物理设计、最优化算法、机器学习等.先后参与了国家自然科学基金、十一五国家“核高基”科技重大专项和新加坡国防科技项目、校企联合项目.E-mail: fbmao@hust.edu.cn" ]
[ "张 宇 男,1987年出生于湖南,华中科技大学计算机科学与技术学院教授,博导,2016年博士毕业于华中科技大学计算机科学与技术学院,主要研究高性能计算、体系结构和系统软件.E-mail: zhyu@hust.edu.cn" ]
[ "廖小飞 男,1978年出生.博士,华中科技大学教授、博士生导师,国家杰出青年基金获得者,“万人计划”科技创新领军人才入选者,中国计算机学会分布式计算与系统专委会主任,华中科技大学科学技术发展院院长.主要从事大数据处理、系统软件、新型体系结构等研究工作.主持或参与多项863重点研发计划、国家自然科学基金项目.在重要期刊和会议上发表100余篇论文,获国家自然科学二等奖1项、国家科技进步二等奖1项、教育部技术发明一等奖2项、教育部自然科学一等奖1项,获2017年度CCF-IEEE CS青年科学家奖.中国电子学会会员编号:E190010157M.E-mail: xfliao@hust.edu.cn" ]
[ "金 海 男,1966年出生.博士,华中科技大学教授、博士生导师,长江学者特聘教授,国家杰出青年基金、CCF“王选奖”获得者,国家“万人计划”科技创新领军人才.中国计算机学会副理事长/会士,IEEE Fellow,华中科技大学“大数据技术与系统国家地方联合工程研究中心”主任,“服务计算技术与系统教育部重点实验室”主任,十四五“先进计算与新兴软件”国家重点研发计划专家组组长,湖北省计算机学会理事长,教育部“长江学者和创新团队发展计划”创新团队学术带头人.主要从事新型体系结构、并行与分布式计算、大数据处理等研究工作.中国电子学会会员编号:E190005379S.E-mail: hjin@hust.edu.cn" ]
收稿:2022-11-01,
修回:2023-05-06,
纸质出版:2024-09-25
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靳晓忠, 刘海坤, 赖皓, 等. 一种可重构异构内存架构和控制器[J]. 电子学报, 2024, 52(09): 3038-3051.
JIN Xiao-zhong, LIU Hai-kun, LAI Hao, et al. A Reconfigurable Heterogeneous Memory Architecture and Memory Controller[J]. Acta Electronica Sinica, 2024, 52(09): 3038-3051.
靳晓忠, 刘海坤, 赖皓, 等. 一种可重构异构内存架构和控制器[J]. 电子学报, 2024, 52(09): 3038-3051. DOI:10.12263/DZXB.20221257
JIN Xiao-zhong, LIU Hai-kun, LAI Hao, et al. A Reconfigurable Heterogeneous Memory Architecture and Memory Controller[J]. Acta Electronica Sinica, 2024, 52(09): 3038-3051. DOI:10.12263/DZXB.20221257
融合传统动态随机访问存储器(Dynamic Random Access Memory,DRAM)与新型非易失性内存(Non-Volatile Memory,NVM)可构建平行架构或层次架构的异构内存系统.平行架构的异构内存系统往往需要通过页迁移技术把热点数据从NVM迁移到DRAM以提高访存性能,然而在操作系统中实现热页监测和迁移会带来巨大的软件性能开销.硬件实现的层次架构由于增加了访存层次,对于访存局部性差的大数据应用反而增加了访存延迟.为此,本文提出可重构的异构内存架构,可以运行时在平行和层次架构间进行转换以动态适配不同应用的访存特性.设计了基于新型指令集架构RISC-V(Reduced Instruction Set Computing-V)的DRAM/NVM异构内存控制器,利用少量硬件计数器实现了访存踪迹统计和分析,并实现了DRAM和NVM物理页间的动态映射和高效迁移机制.实验表明,DRAM/NVM异构内存控制器可提高43%的应用性能.
Heterogeneous memory systems composed of traditional dynamic random access memory (DRAM) and new non-volatile memory (NVM) can be organized in a horizontal architecture or a hierarchical architecture. The horizontal DRAM/NVM architecture often requires page migration technologies to improve memory access performance. However
hot page monitoring and migration implemented in operating systems would cause significant software performance overhead. The hardware-supported hierarchical architecture even increases the memory access latency for big data applications with poor data locality due to the deeper memory hierarchy. To this end
this paper proposes a reconfigurable heterogeneous memory architecture that can be converted between horizontal and hierarchical architectures at runtime to dynamically adapt the memory access characteristics of different applications. We design a DRAM/NVM heterogeneous memory controller (HMC) based on the new instruction set architecture RISC-V (Reduced Instruction Set Computing-V). The HMC uses a few hardware counters for memory access monitoring and analyzing
and achieves dynamic address mapping and efficient page migration between DRAM and NVM pages. Experimental results show that the DRAM/NVM hybrid memory controller can improve application performance by 43%.
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