200 V全碳化硅集成技术

顾勇; 马杰; 刘奥; 黄润华; 刘斯扬; 柏松; 张龙; 孙伟锋

doi:10.12263/DZXB.20230782

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200 V全碳化硅集成技术

学术论文 | 更新时间：2025-12-24

- 200 V全碳化硅集成技术
- 200 V All-SiC Integration Technology
- 电子学报 2024年52卷第7期页码：2183-2189
- 作者机构：
  
  1.东南大学集成电路学院，江苏南京 210096
  2.南京电子器件研究所，江苏南京 210016
- 作者简介：
  
  [ "顾勇男，1996年2月出生.东南大学博士研究生.主要研究方向为碳化硅半导体集成工艺及器件." ]
  [ "马杰男，1995年4月出生.东南大学博士后.主要研究方向为碳化硅半导体集成工艺及器件." ]
  [ "刘斯扬男，1987年出生.东南大学博士后，东南大学青年首席教授，博士生导师. 主要研究方向为功率半导体集成工艺及器件.中国电子学会会员编号：E190029952M.E-mail: liusy2017@seu.edu.cn" ]
  [ "张龙男，1986年出生.东南大学博士后，副高级职称，博士生导师.主要研究方向为功率半导体集成工艺及器件.中国电子学会会员编号：E190022693S." ]
  [ "孙伟锋男，1977年出生，江苏武进人. 2000年、2003年、2007年于东南大学分别获得学士、硕士及博士学位.目前为东南大学首席教授，国家高层次人才，江苏特聘教授，博士生导师.主要研究方向为功率集成电路.中国电子学会会员编号：E190009272S.E-mail: swffrog@seu.edu.cn" ]
- 基金信息：
  
  国家自然科学基金(62274032;62174029);江苏省科技成果转化专项资金项目(BA2022005)
- DOI：10.12263/DZXB.20230782
  中图分类号： TN305;TN432
- 收稿：2023-08-15，
  
  修回：2024-02-02，
  
  纸质出版：2024-07-25
- 稿件说明：
移动端阅览
顾勇, 马杰, 刘奥, 等. 200 V全碳化硅集成技术[J]. 电子学报, 2024, 52(07): 2183-2189.

GU Yong, MA Jie, LIU Ao, et al. 200 V All-SiC Integration Technology[J]. Acta Electronica Sinica, 2024, 52(07): 2183-2189.
顾勇, 马杰, 刘奥, 等. 200 V全碳化硅集成技术[J]. 电子学报, 2024, 52(07): 2183-2189. DOI：10.12263/DZXB.20230782

GU Yong, MA Jie, LIU Ao, et al. 200 V All-SiC Integration Technology[J]. Acta Electronica Sinica, 2024, 52(07): 2183-2189. DOI：10.12263/DZXB.20230782

摘要

本文提出了一种基于N衬底P外延晶圆的全碳化硅（Silicon Carbide，SiC）集成工艺平台，该工艺平台兼容低压互补金属氧化物半导体场效应晶体管（Complementary Metal Oxide Semiconductor field-effect transistor，CMOS）、横向扩散金属氧化物半导体（Laterally-Diffused MOS，LDMOS）以及高压二极管等器件.采用P型缓冲层技术调节器件垂直方向电场分布，使高压器件垂直方向耐受电压提高212.4%；在1 μm厚度的P型缓冲层和1 μm厚度的P型外延层上，实现LDMOS、高压二级管和高侧区域耐受电压大于300 V.基于该工艺平台，搭建了SiC CMOS反相器和反相器链电路，均实现了0~20 V轨至轨的电压输出；设计了半桥驱动电路，低压侧驱动电路由四阶反相器构成；高压侧驱动电路由电平移位电路和高侧区域反相器链电路组成，实现了180~200 V浮空栅极驱动信号输出.

Abstract

An all silicon carbide integrated process platform based on the wafer with N-substrate and P-epitaxy is proposed in this paper

which is compatible with CMOS (Complementary Metal Oxide Semiconductor field-effect transistor) devices

LDMOS (Laterally-Diffused MOS) and high-voltage diodes. A P-buffer layer is adopted to modulate the vertically distributed electric field and potential

which results in 212.4% improvement in vertical voltage withstanding. The LDMOS

high voltage diode and high side region can achieve more than 300 V breakdown voltage in 2 μm P-type epitaxial layer. Based on this platform

SiC (Silicon Carbide) CMOS inverter and inverter chain are constructed

all of which achieve voltage output ranging from 0~20 V with rail-to-rail capability. A half-bridge driving circuit is designed with a four-stage inverter chain as the low-side driver circuit. The high-side driver circuit consists of level-shifting circuit and a high-side region inverter chain circuit

producing an output of 180~200 V floating gate drive signal.

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Keywords

references

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