1 500 V超结功率MOS器件优化与电容特性研究

种一宁; 李珏; 乔明

doi:10.12263/DZXB.20230845

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1 500 V超结功率MOS器件优化与电容特性研究

学术论文 | 更新时间：2025-12-24

- 1 500 V超结功率MOS器件优化与电容特性研究
- Optimization and Capacitance Characteristics of 1 500 V Super Junction Power MOS Devices
- 电子学报 2024年52卷第7期页码：2271-2278
- 作者机构：
  
  1.电子科技大学电子薄膜与集成器件全国重点实验室,四川成都 611731
  2.电子科技大学广东电子信息工程研究院,广东东莞 523950
  3.电子科技大学(深圳)高等研究院,广东深圳 518110
- 作者简介：
  
  [ "种一宁女，2000年12月出生，河北辛集人.电子科技大学集成电路科学与工程学院本科生.主要研究方向为功率半导体器件和微机械系统.E-mail: cyn20001202@163.com" ]
  [ "李珏女，1997年10月出生，甘肃定西人.电子科技大学集成电路科学与工程学院研究生.主要研究方向为功率器件.E-mail: 957799800@qq.com" ]
  [ "乔明男，1981年3月出生，辽宁葫芦岛人.电子科技大学教授、博士生导师.主要研究方向为功率半导体器件、BCD集成技术、高压功率集成电路、功率器件可靠性、抗辐射功率器件及高压集成技术、高压ESD防护技术、功率器件建模.中国电子学会会员编号：E190013004S.E-mail: qiaoming@uestc.edu.cn" ]
- 基金信息：
  
  广东省基础与应用基础研究基金(2021B1515020031);国家自然科学基金(62174024);航空科学基金(201943080002)
- DOI：10.12263/DZXB.20230845
  中图分类号： TN323.4;
- 收稿：2023-09-07，
  
  修回：2023-11-25，
  
  纸质出版：2024-07-25
- 稿件说明：
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种一宁, 李珏, 乔明. 1 500 V超结功率MOS器件优化与电容特性研究[J]. 电子学报, 2024, 52(07): 2271-2278.

CHONG Yi-ning, LI Jue, QIAO Ming. Optimization and Capacitance Characteristics of 1 500 V Super Junction Power MOS Devices[J]. Acta Electronica Sinica, 2024, 52(07): 2271-2278.
种一宁, 李珏, 乔明. 1 500 V超结功率MOS器件优化与电容特性研究[J]. 电子学报, 2024, 52(07): 2271-2278. DOI：10.12263/DZXB.20230845

CHONG Yi-ning, LI Jue, QIAO Ming. Optimization and Capacitance Characteristics of 1 500 V Super Junction Power MOS Devices[J]. Acta Electronica Sinica, 2024, 52(07): 2271-2278. DOI：10.12263/DZXB.20230845

摘要

本文利用半超结结构进行高压超结功率金属氧化物半导体（Metal Oxide Semiconductor，MOS）器件的设计，基于Sentaurus TCAD（Technology Computer Aided Design）仿真平台设计超结元胞结构并优化高压超结功率MOS器件的击穿电压与导通电阻，随后探究了寄生电容的特性.最后，基于多次外延工艺自主设计出一款器件结构仿真击穿电压1 658 V、工艺仿真击穿电压1 598 V、比导通电阻

值303 mΩ·cm

的高压超结功率MOS器件，与相同耐压值器件相比，比导通电阻值下降约50%.同时探究了超结掺杂浓度与厚度以及电压支持层掺杂浓度与厚度4个主要结构参数对器件寄生电容特性的影响.

Abstract

In this paper

the design of high-voltage super junction power MOS (Metal Oxide Semiconductor) device is carried out by using the semi-super junction structure

the super junction cell structure is designed based on the Sentaurus TCAD (Technology Computer Aided Design) simulation platform

and the breakdown voltage and on-resistance of the high-voltage super junction power MOS devices are optimized

and then the characteristics of parasitic capacitance are explored. Finally

based on multiple epitaxial processes

a high-voltage super junction power MOS device with a simulated breakdown voltage of 1 658 V

a process simulation breakdown voltage of 1 598 V and a specific on-resistance value of 303 mΩ·cm

has been independently designed

which reduced the specific on-resistance value by about 50% compared with the same withstand voltage device. At the same time

the influence of four main structural parameters

namely super junction doping concentration and thickness and voltage support layer doping concentration and thickness

on the parasitic capacitance characteristics of the device has been explored.

关键词

Keywords

references

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