基于动态电容的复合电流源阶段延时计算方法

郭静静; 查佩文; 张树钢; 蔡志匡

doi:10.12263/DZXB.20241149

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基于动态电容的复合电流源阶段延时计算方法

学术论文 | 更新时间：2025-12-10

- 基于动态电容的复合电流源阶段延时计算方法
- Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance
- 电子学报 2025年53卷第7期页码：2428-2440
- 作者机构：
  
  南京邮电大学集成电路科学与工程学院（产教融合学院），江苏南京 210023
- 作者简介：
  
  [ "郭静静女，1989年1月出生于山西省大同市.2011年和2014年毕业于西安电子科技大学，获得微电子学学士学位和集成电路工程硕士学位.2020年毕业于东南大学，获得微电子学与固体电子学博士学位.现任南京邮电大学讲师.主要研究方向为统计时序分析.E-mail: guo625jingjing@njupt.edu.cn" ]
  [ "查佩文男，1998年出生于江苏省南京市，硕士.2021年进入南京邮电大学集成电路科学与工程学院.主要研究方向为静态时序分析、复合电流源模型.E-mail: 18851820500@163.com" ]
  [ "张树钢男，2001年出生于山东省滨州市.2023年进入南京邮电大学集成电路科学与工程学院，在读硕士研究生.主要研究方向为静态时序分析. E-mail: 1223228018@njupt.edu.cn" ]
  [ "蔡志匡男，1983年出生于江苏省连云港市.2014年毕业于东南大学电子科学与工程学院.现任南京邮电大学集成电路科学与工程学院教授、博士生导师.主要研究方向为低功耗集成电路设计与测试.中国电子学会会员编号：E190019695S.E-mail: whczk@njupt.edu.cn" ]
- 基金信息：
  
  江苏省自然科学基金(BK20240637)
- DOI：10.12263/DZXB.20241149
  中图分类号： TN47;TN401
- 收稿：2024-12-20，
  
  修回：2025-06-24，
  
  纸质出版：2025-07-25
- 稿件说明：
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郭静静, 查佩文, 张树钢, 等. 基于动态电容的复合电流源阶段延时计算方法[J]. 电子学报, 2025, 53(07): 2428-2440.

GUO Jing-jing, ZHA Pei-wen, ZHANG Shu-gang, et al. Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance[J]. Acta Electronica Sinica, 2025, 53(07): 2428-2440.
郭静静, 查佩文, 张树钢, 等. 基于动态电容的复合电流源阶段延时计算方法[J]. 电子学报, 2025, 53(07): 2428-2440. DOI：10.12263/DZXB.20241149

GUO Jing-jing, ZHA Pei-wen, ZHANG Shu-gang, et al. Composite Current Source Stage Delay Calculation Method Based on Dynamic Capacitance[J]. Acta Electronica Sinica, 2025, 53(07): 2428-2440. DOI：10.12263/DZXB.20241149

摘要

深亚微米工艺下传统时序模型的延时计算不再准确，针对米勒效应愈发不可忽视、互连线电阻性增大和互连线延时比重越来越大等问题，本文提出一种基于动态电容的复合电流源阶段延时计算方法.首先，本文引入基于电压的插值方法支持复合电流源的延时计算；其次，构建Π模型为负载的单元延时计算方法，采用多阈值分析改进有效电容并推导动态电容，实现迭代计算流程；随后，扩展动态电容概念到阶段延时计算中，实现以分布式RC网络作为负载的阶段延时计算方法，并使用机器学习优化互连线延时.基于ASAP 7 nm Predictive PDK （ASAP 7）工艺，本文提出的阶段延时计算方法与SPICE（Simulation Program with Integrated Circuit Emphasis）对比分别实现了1.49%、3.16%、1.70%、0.88%的单元延时、单元转换时间、互连线延时与互连线转换时间的平均相对误差，平均在4~5次迭代后达到收敛.

Abstract

With the deep sub-micron technology in integrated circuit develops

Miller effect becomes non-negligible and the increasing interconnection resistivity increases

leading to increased delay time prediction inaccuracy. A composite current source stage delay calculation method based on dynamic capacitance is proposed in this paper. A voltage-based interpolation method is firstly introduced to support the delay calculation of composite current source. A cell delay calculation method with a Π model load is then established and a multi-threshold analysis is used to improves the effective capacitance

derives the dynamic capacitance and realizes the iterative calculation process. The dynamic capacitance concept is applied to the stage delay calculation

and used to realize the stage delay calculation method with distributed RC network as the load. By using machine learning

the interconnect wire delay is further optimized. Based on the ASAP 7 nm predictive PDK (ASAP 7) technology

the stage delay calculation method proposed in this paper achieves an average relative error of 1.49%

3.16%

1.70%

and 0.88% for the cell delay

cell transition time

interconnect line delay

and interconnect line transition time

respectively

compared with simulation program with integrated circuit emphasis (SPICE) simulation

the stage delay calculation method reaches convergence with about 4~5 iterations.

关键词

Keywords

references

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