基于动态频段检测的多频同步系统设计与实现

郑辰; 万凯; 吴泳澎

doi:10.12263/DZXB.20251137

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基于动态频段检测的多频同步系统设计与实现

更新时间：2026-05-15

- 基于动态频段检测的多频同步系统设计与实现
- Implementation of a Multi-frequency Synchronization System Based on Dynamic Band Detection
- 电子学报 2026年页码：1-17
- 作者机构：
  
  1.上海交通大学集成电路学院，上海 200240
  2.国家电网有限公司信息通信中心（大数据中心），北京 100761
- 作者简介：
  
  [ "郑辰男，2000年12月出生于上海市。现为上海交通大学集成电路学院在读硕士研究生。主要研究方向为电力线载波通信。 E-mail: zhengchen@sjtu.edu.cn" ]
  [ "万凯男，1985年12月出生于江西省南昌市，2014年毕业于英国诺丁汉大学电子与电气工程专业。现为国家电网有限公司信息通信中心（大数据中心）高级工程师，主要研究方向为人工智能与物联网技术应用。 E-mail: kai-wan@sgcc.com.cn" ]
  [ "吴泳澎男，1986年5月出生于江西省南昌市。现为上海交通大学教授。主要研究方向为安全、超可靠和低时延通信理论与方法研究。 E-mail: yongpeng.wu@sjtu.edu.cn" ]
- 基金信息：
- DOI：10.12263/DZXB.20251137
  中图分类号： TN914;
- 收稿：2026-03-02，
  
  录用：2026-04-01，
  
  网络首发：2026-05-15，
- 稿件说明：
移动端阅览
郑辰, 万凯, 吴泳澎. 基于动态频段检测的多频同步系统设计与实现[J/OL]. 电子学报, 2026,1-17.

ZHENG Chen, WAN Kai, WU Yongpeng. Implementation of a Multi-frequency Synchronization System Based on Dynamic Band Detection[J/OL]. ACTA ELECTRONICA SINICA, 2026, 1-17.
郑辰, 万凯, 吴泳澎. 基于动态频段检测的多频同步系统设计与实现[J/OL]. 电子学报, 2026,1-17. DOI： 10.12263/DZXB.20251137.

ZHENG Chen, WAN Kai, WU Yongpeng. Implementation of a Multi-frequency Synchronization System Based on Dynamic Band Detection[J/OL]. ACTA ELECTRONICA SINICA, 2026, 1-17. DOI： 10.12263/DZXB.20251137.

摘要

频分电力线载波通信（Frequency Division Power Line Communication， FD-PLC）技术以其灵活的多频段通信能力与高效的前导竞争接入机制，有效解决了工业物联网本地通信网络中由电力线信道复杂环境引起的通信可靠性与组网效率问题，但现有FD-PLC节点硬件实现存在资源占用高、功耗大的问题，难以满足工业物联网通信节点低成本、低功耗的实际需求。针对上述问题，本文提出一种基于动态频段检测的多频同步系统，将传统多路并行检测结构重构为频谱实时感知与单通道同步检测相结合的实现方式，在保持同步性能基本不变的前提下降低硬件实现复杂度。该系统采用流水线式快速傅里叶变换实现实时功率谱分析，通过信号功率谱与背景噪声谱的归一化除法运算计算各频段内归一化功率累积值，完成动态的信号频段盲检测，再通过改进的定时机制与峰值搜索算法完成帧同步。本文在典型电力线多径信道以及背景噪声、脉冲噪声和窄带干扰等条件下建立仿真模型，并引入实测电力线噪声对系统性能进行验证，同时与传统FD-PLC 8路并行检测结构进行了对比。结果表明，在高信噪比条件下，所提系统的同步性能与传统方案基本一致，在低信噪比及多种非平稳噪声条件下，同步性能退化不超过1 dB，虚警性能与传统并行架构保持高度一致，并在窄带干扰和实测噪声条件下表现出良好的鲁棒性。复杂度分析结果表明，该方案在仅引入约3.43%额外带宽开销的前提下，持续监听阶段的实数加法与乘法开销分别降低54%和57%，捕获阶段分别降低23%和28%。进一步地，本文在Altera公司Cyclone Ⅳ E系列现场可编程门阵列（Field-Programmable Gate Array， FPGA）上完成了系统实现。综合结果显示，与传统8路并行检测方案相比，所提系统总逻辑元件占用降低72%，组合逻辑函数降低73%，专用逻辑寄存器降低75%，嵌入式9位乘法器减少62%，总功耗下降40%。研究结果表明，所提系统在同步性能、计算复杂度与硬件资源之间实现了有效平衡，适用于工业物联网场景下FD-PLC通信节点的大规模、低成本和低功耗部署。

Abstract

Frequency Division Power Line Communication(FD-PLC) technology effectively addresses the communication reliability and networking efficiency issues caused by the complex power line channel environment in local Industrial Internet of Things(IIoT) communication networks

owing to its flexible multi-band communication capability and efficient preamble-based contention access mechanism. However

existing hardware implementations of FD-PLC nodes suffer from high resource consumption and power dissipation

making them difficult to meet the practical requirements of low-cost and low-power IIoT communication nodes. To address this problem

this paper proposes a multi-frequency synchronization system based on dynamic band detection

which reconstructs the conventional multi-channel parallel detection architecture into an implementation combining real-time spectrum sensing and single-channel synchronization detection

thereby reducing hardware implementation complexity while maintaining nearly unchanged synchronization performance. The proposed system employs a pipelined Fast Fourier Transform(FFT) to achieve real-time power spectrum analysis. By performing a normalized division operation between the signal power spectrum and the background noise spectrum

the normalized accumulated power within each frequency band is calculated to realize dynamic blind detection of the signal band. Frame synchronization is then accomplished through an improved timing mechanism and a peak search algorithm. Simulation models are established under typical power line multipath channels as well as background noise

impulsive noise

and narrowband interference conditions. Measured power line noise is further introduced to validate the system performance

and comparisons are conducted with the conventional eight-channel parallel detection architecture for FD-PLC. The results show that

under high signal-to-noise ratio(SNR) conditions

the synchronization performance of the proposed system is basically consistent with that of the conventional scheme. Under low-SNR and various non-stationary noise conditions

the synchronization performance degradation is no more than 1 dB

the false alarm performance remains highly consistent with that of the conventional parallel architecture

and the proposed system exhibits good robustness under both narrowband interference and measured noise conditions. Complexity analysis shows that

with only about 3.43% additional bandwidth overhead

the proposed scheme reduces the numbers of real additions and real multiplications in the continuous monitoring stage by about 54% and 57%

respectively

and reduces those in the capture stage by about 23% and 28%

respectively. Furthermore

the proposed system is implemented on an Altera Cyclone Ⅳ E Field-Programmable Gate Array(FPGA) platform. Comprehensive results indicate that

compared with the conventional eight-channel parallel detection scheme

the proposed system reduces total logic element usage by about 72%

combinational logic functions by about 73%

dedicated logic registers by about 75%

embedded 9-bit multipliers by about 62%

and total power consumption by about 40%. The results demonstrate that the proposed system achieves an effective balance among synchronization performance

computational complexity

and hardware resource consumption

making it suitable for large-scale

low-cost

and low-power deployment of FD-PLC communication nodes in IIoT scenarios.

关键词

Keywords

references

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