Test wrapper

which to make IP cores in SOC measurable and controllable

is the key architecture

and its important part is wrapper cell. Traditional test wrapper has many shortcomings

such as parallel test

test secure and test power

when used in hierarchical SOCs. This paper presented a modified test wrapper design for embedded IP cores

which only inserted a CMOS transmission gate to the test wrapper cell to eliminate the precarious effect to IP cores

to make the IP cores dormancy. Experiments on an industry hierarchical SOCs show that the proposed test wrapper cell not only takes less area overhead and time delay

but also make test parallel

secure and fully

thus decreases the dynamic test power during scan shifting.