This paper proposes a pre-execution directed prefetching(PEDP) method to improve the memory latency tolerance of in-order processors.PEDP utilizes stride prefetching to handle regular access patterns and pre-execution to generate accurate prefetches regardless of the regularity of access patterns when a L2 cache miss occurs

which combines the advantages of the two techniques to improve the prefetch coverage.Meanwhile

PEDP captures actual memory access patterns during pre-execution to guide the stride prefetcher's update process.Under the guide of pre-execution

the stride prefetcher can issue prefetches earlier than pre-execution for addresses that can be generated by both of the two techniques

thus improving the prefetch timeliness.In addition

PEDP achieves improvement in prefetch accuracy by an update filter which effectively eliminates the harmful updates to the stride prefetcher during the guide process.Experimental results demonstrate that PEDP increases the performance by 33.0% over the baseline processor.Compared with stride prefetching and pre-execution

PEDP improves the performance by 16.2% and 7.3%

respectively.