12.5 Gb/s half-rate clock and data recovery (CDR) circuit and 1:2 demultiplexer(DEMUX) applied to a serializer/deserializer (SerDes) receiver were designed and implemented in 0.18m CMOS process.The CDR and DEMUX provided 6.25 GHz clock and 6.25 Gb/s data for the SerDes receiver.The circuit incorporated a Bang-bang phase/frequency detector (PFD)

a four-stage ring voltage-controlled oscillator (VCO)

a V/I (Voltage-to-Current) converter

a low pass filter (LPF)

a 1:2 DEMUX and so on.A new half-rate PFD which sampled the clock by data was adopted

and this PFD could increase operating

rate up to 12.5 Gb/s.The tested results show that at the supply voltage of 1.8V

the tune range of VCO is about 1GHz at 6.25GHz centre frequency.When the data rate of the input pseudorandom is 12Gb/s and sequence length is 2

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the recovered 6GHz clock has a root mean square (RMS) jitter of 1.9ps and a peak-to-peak jitter of 9.12ps.At the same time

the total chip can work well and the eye diagram of output data is clear.The die size is 0.4760.538 mm

2

and the core power consumption is only 150mW excluding the output buffers.