CAI Shuo, KUANG Ji-shun, LIU Tie-qiao, et al. Reliability Calculation Method of Logic Circuits Considering Signal Correlation[J]. Acta Electronica Sinica, 2014, 42(8): 1660-1664.
CAI Shuo, KUANG Ji-shun, LIU Tie-qiao, et al. Reliability Calculation Method of Logic Circuits Considering Signal Correlation[J]. Acta Electronica Sinica, 2014, 42(8): 1660-1664. DOI: 10.3969/j.issn.0372-2112.2014.08.032.
As the feature size of integrated circuits shrinks
soft errors become the key factor influencing circuit reliability.Calculation of signal probability of logic circuits affected by soft errors can assist us in evaluating the circuit reliability.The reconvergent fanouts in circuits increase computational complexity of signal probability.A reliability calculation method of logic circuits is proposed in this paper.The method uses the probability formula and polynomial arithmetic
then the fanout source variables which trigger signal correlation are reduced.Based on this
the circuit reliability can be evaluated by the output signal probability.Experimental results on LGSynth91
74X series and ISCAS85 benchmark circuits show that our method is accurate and efficient.