WANG Peng-jun, ZHANG Xue-long, ZHANG Yue-jun. Design of Highly Robust PUF Based on the Optimal Gate Voltage[J]. Acta Electronica Sinica, 2015, 43(5): 907-910.
WANG Peng-jun, ZHANG Xue-long, ZHANG Yue-jun. Design of Highly Robust PUF Based on the Optimal Gate Voltage[J]. Acta Electronica Sinica, 2015, 43(5): 907-910. DOI: 10.3969/j.issn.0372-2112.2015.05.011.
extract key relying upon the intrinsic process variations in silicon devices.This paper proposes a scheme of highly robust PUF.First
we analyze the properties of the MOSFET working at the point of Zero Temperature Coefficient.And then we determine the structure and the optimal gate voltage of PUF by combining the approaches that improve the robustness of PUF circuits.All of which lead to the goal of making the keys stable and reliable at last.This design is implemented in TSMC 65nm CMOS technology and the layout area occupies 14.89
m12.14
m. The simulation results show that the reliability of PUF is not less than 96%