The optimization problem of three dimensional system on chip (SoC) needs to be solved before it enters the market.We propose a reconfigured test architecture optimization of TSV-based (Through Silicon Vias-based) 3D SoC

and the optimization includes both mid-bond testing and post-bond testing.As both test time and the number of TSV for test impact the overall test cost

our proposed scheme can reduce overall test time

while controlling the number of TSVs.Experiment results show that our scheme achieves around 20% on the reduction of test cost compared with one baseline solution which only considers reducing test time.