According to the experimental measurement results

combining with the technology computer aided design (TCAD) simulations

the hot-carrier degradations of 1.8V pMOS under different gate voltages are investigated in this paper.The results show that

with the gate voltage increasing

the electron injection mechanism changes to the hole injection mechanism

leading to the increases of the saturation drain current (I

dsat

)

linear drain current (I

dlin

) and threshold voltage (

V

th

).However

because there is not any carrier injection

the de

gradation trend begins to change at

V

gs

=90%*V

ds

.Moreover

the study also discovers that the generated interface states have more impact on the hole mobility in the depletion region than that in the non-depletion region.As a result

the degradation of forward I

dsat

is bigger than the degradation of reverse I

dsat

.However

the degradations of forward I

dlin

and reverse I

dlin

are same since the whole channel is not depleted under I

dlin

condition.