This paper presents an approach to improve the efficiency of the Doherty power amplifier.To mitigate the efficiency degradation resulting from the imperfect load modulation and the knee voltage effect

the requirements that the load impedances of the carrier and peaking transistors should meet were outlined.Subsequently

a constant voltage standing wave ratio (VSWR) circle that was related to the carrier amplifier's load impedances was derived and utilized to obtain the carrier transistor's optimum load impedances.For experimental validation

an asymmetrical DPA operating at 2.35GHz was designed and implemented.Tested with single tone continuous wave

the proposed DPA delivers a saturation power of about 49.3dBm and exhibits a drain efficiency of higher than 68% and 55% at peak and 8dB back-off power

respectively.When driven with 5 carriers 100MHz LTE-advanced signal

the DPA shows an average efficiency of 50.5% at 40.5dBm output power

along with an adjacent channel leakage ratio (ACLR) of lower than -47.5dBc after the digital pre-distortion (DPD) correction.The experimental results demonstrated that the proposed Doherty power amplifier has high average efficiency and good linearity performance

which verified the effectiveness of the proposed design approach.