A low-latency parallel WOLA (Weighted Overlap-add) DFT filter bank design method and its implementation on FPGA are presented. System objective function combined with group delay

asymmetric synthesis window design and iterative algorithm are adopted to reduce the overall system delay during the optimization of DFT filter banks. Calculation delay of FPGA implementation is controlled through multichannel parallel multiplication

multistage pipeline addition chain in key modules of DFT filter banks. The whole design is implemented on a Xilinx FPGA chip of Zynq7020. PESQ test shows that the design can achieve good speech quality. Compared with the serial WOLA structure

the delay of parallel WOLA can be reduced by 1. 192 ms at 16 kHz speech sampling rate

with the group delay reduced by 12% and the calculation delay reduced by 29. 2%.