The arithmetic cell

especially the multiplier

is one of the key components of the modern digital systems

which could affect the efficiency of the whole system dramatically. In this article

we propose an extended Booth algorithm

which is different from the traditional one with the strategy of keeping all the partial products during shifting

then compressing and finally summing. This new one could reduce the coupling of each function and simplify the control part of the circuit. Moreover

by following the asynchronous design methodology

the control circuit with the Click based asynchronous micro pipeline that obeys a two-phase handshake protocol with "bounded bundle data" is implemented. With the policy of isolating data processing from control

an 8-bit asynchronous multiplier is designed and then implemented with FPGA. With the FPGA of 45nm technology and the same architecture

this asynchronous Booth multiplier is over 12 times faster than the synchronous one while keeping the area and power almost same.