1. 中国科学院微电子研究所,北京,100029
2. 北方工业大学,北京,100144
3. 中国科学院微电子研究所,北京,100029
4. 北方工业大学,北京,100144
网络出版:2018-08-25,
纸质出版:2018
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白文帅, 武锦, 吴旦昱, 等. 基于FPGA的超高速时间交织ADC后台校准技术[J]. 电子学报, 2018,46(8):2020-2025.
BAI Wen-shuai, WU Jin, WU Dan-yu, et al. Background Calibration Technology for High Speed Time-Interleaved ADC Based on FPGA[J]. Acta Electronica Sinica, 2018, 46(8): 2020-2025.
白文帅, 武锦, 吴旦昱, 等. 基于FPGA的超高速时间交织ADC后台校准技术[J]. 电子学报, 2018,46(8):2020-2025. DOI: 10.3969/j.issn.0372-2112.2018.08.030.
BAI Wen-shuai, WU Jin, WU Dan-yu, et al. Background Calibration Technology for High Speed Time-Interleaved ADC Based on FPGA[J]. Acta Electronica Sinica, 2018, 46(8): 2020-2025. DOI: 10.3969/j.issn.0372-2112.2018.08.030.
针对时间交织模数转换器(TI-ADC)三项主要失配误差(采样时间间隔失配误差、偏移失配误差和增益失配误差),提出一种基于FPGA的数字后台校准技术.失配误差值可通过校准算法得出,此校准算法基于统计近似的数学方法.反馈调节被用来减少TI-ADC的三项主要失配误差.此技术采用片外校准方式,校准算法在FPGA内部完成,校准调节电路在TI-ADC内部完成.实验结果表明:TI-ADC校准后与校准前比较,平均有效位数(ENOB)和平均无杂散动态范围(SFDR)分别提高0.58和11.28dBc,验证了该后台校准技术的有效性.
Due to the time interleaved analog-to-digital converter (TI-ADC) existing three major mismatch error (the sampling time interval mismatch error
offset mismatch error and gain mismatch error)
a digital background calibration technique based on FPGA is proposed.The mismatch error can be obtained by the calibration algorithm
which is based on the mathematical method of statistical approximation.Feedback regulation is used to reduce the three major mismatch errors of TI-ADC.This technology adopts off chip calibration
calibration algorithm is completed in the FPGA
and the calibration control circuit is completed in TI-ADC.The experimental results show that the average effective number (ENOB) and the average spurious free dynamic range (SFDR) are improved by 0.58 and 11.28dBc respectively.The effectiveness of the proposed background calibration technique is verified.
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