中国电子科技集团公司第十三研究所,河北,石家庄,050051
网络出版:2018-08-25,
纸质出版:2018
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刘佳佳, 刘英坤, 谭永亮, 等. 基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET[J]. 电子学报, 2018,46(8):2026-2029.
LIU Jia-jia, LIU Ying-kun, TAN Yong-liang, et al. 1.2kV 4H-SiC DMOSFET with Phosphorous Passivated Gate Dielectric[J]. Acta Electronica Sinica, 2018, 46(8): 2026-2029.
刘佳佳, 刘英坤, 谭永亮, 等. 基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET[J]. 电子学报, 2018,46(8):2026-2029. DOI: 10.3969/j.issn.0372-2112.2018.08.031.
LIU Jia-jia, LIU Ying-kun, TAN Yong-liang, et al. 1.2kV 4H-SiC DMOSFET with Phosphorous Passivated Gate Dielectric[J]. Acta Electronica Sinica, 2018, 46(8): 2026-2029. DOI: 10.3969/j.issn.0372-2112.2018.08.031.
本文对比了NO退火和磷掺杂两种栅钝化工艺,其中磷钝化采用了平面扩散源进行掺杂,通过C-V特性进行了4H-SiC/SiO
2
界面特性评价,使用Terman法分析计算获得距导带底0.2-0.4eV范围内界面态密度.结果表明引入磷比氮能更有效降低界面态密度,提高沟道载流子迁移率.其次,对比了两种栅钝化工艺制备的4H-SiC DMOSFET器件性能,实验表明采用磷钝化工艺处理的器件性能更优.最后,基于磷掺杂钝化工艺首次制备出击穿电压为1200V、导通电阻为20m、漏源电流为75 A、阈值电压为2.4V的4H-SiC DMOSFET.
To improve the 4H-SiC/SiO
2
interface quality phosphorous-doped technology and nitrogen-annealed technology were introduced.The phosphorous atoms were introduced into the 4H-SiC/SiO
2
interface by thermal annealing with a planar diffusion source (PDS).Current-voltage test was used to characterize the interface quality.To obtain the interface state density (
D
it
) lying energetically within 0.2eV-0.4eV of the conduction band edge (
E
c
)
the C-V data was analyzed by using Terman method.It is apparent that the phosphorous-doped technology can reduce the interface state density near the conduction band of 4H-SiC effectively and increase the channel mobility and decrease the on resistanc
e.Compared with NO passivated devices
P-doped devices have better performance.What's more
this technology has been applied to fabricate 1.2kV 4H-SiC DMOSFET firstly.Fabricated devices show a significant improvement with an on resistance of 20m
drain-source current of 75A
threshold voltage of 2.4V.
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