Considering the transistors distribution in a SRAM and the relative positions of two adjacent SRAMs

the mechanism of multiple upsets in 65nm twin-well CMOS SRAM internal nodes and the impact factors of multiple cell upset induced by parasitic bipolar effect are investigated through 3D TCAD device simulation. It is found that multiple upsets in SRAM internal nodes result from the competition of p

+

-drains in the n-well. The competition depends on the parasitic bipolar effect which is related to the distan

ce between p

+

-source and n-well contact

as well as the electric potential difference between p

+

-drain and n-well. PNP parasitic bipolar transistors play an important role in nanometric twin-well CMOS SRAM. Although reducing the distance between SRAM and n-well contact can weaken parasitic bipolar effect

ions with special incident angles or high linear energy transfers can also trigger the parasitic bipolar effect in adjacent SRAM and induce multiple cell upset.