In this paper

a multi-model based floorplanner named UPRFloor is proposed to save reconfigurable resources and reduce communication overhead during the floorplanning of FPGAs. According to the shape of logical functions

a description model which can depict both rectangular and non-rectangular shapes is firstly defined. Then

the Mixed-Integer Linear Programming (MILP) ideology is used to optimize an objective function which takes the waste of resources and all kinds of communication costs into account to obtain a desirable floorplan. Finally

the UPRFloor strategy has been simulated on FPGA chips and the results show that the strategy saves reconfigurable resources as much as 25.59%. The proposed method is validated on the data set from MCNC standard benchmark. The UPRFloor reduces 22.49% global wire length at most with almost the same time-consuming as other algorithms. Experiments conducted on the SDR design also demonstrate that the strategy saves reconfigurable resources as much as 29.41% and reduces 13.41% global wire length at most

which effectively reduces the wasting of resources the communication cost.