Aiming at the optimization of advanced encryption standard (AES) S-box

an enhanced delay-aware common subexpression elimination algorithm is proposed.Under different delay constraints

the proposed algorithm can not only optimize multiple constant multiplication circuit

but also provide all of the design trade-offs

from the shortest feasible delay to the smallest area.Two constructions of S-box based on redundant finite field arithmetic which have optimal delay or the optimal area are derived using the algorithm.The results obtained through optimizing examples show the algorithm achieves high optimization efficiency and better overall delay optimization effect.In 65nm CMOS technology

the proposed S-box circuit which has the optimal area has the minimum area-delay product among the S-boxes based on composite field architecture.Compared with the smallest S-box and the shortest delay S-box

it saves about 17.58% and 19.74% of the area-delay product respectively.