In order to reduce the output distortion that caused by the non-constant group delay of digital filter

an equalization based optimization technique is proposed

in this paper

for decreasing the variation of group delay in cascaded infinite-impulse response digital filter. By inserting all-pass equalizer behind each stage of the cascaded ⅡR digital filter

the variation of group delay within the passband range can be reduced

and the output distortion of the digital filter can also be decreased. For the group delay optimization method proposed in this paper

when the 1st and 2nd order equalizers are used for circuit optimization

the variation of group delay is reduced by 28.19% and 49.

93% respectively in the passband range of 0~100Hz. Based on the 0.18μm CMOS standard cell library for logic synthesis and layout design

the area of the entire filter circuit IP core layout is 0.1747mm

2

. Compared with the existing literature methods

this method has a significant effect on group delay optimization

and the power consumption and area are small in circuit implementation

which is very suitable for system-on-chip applications.