Approximate computing is a novel way in logic circuit design which offers the savings of the power

area and delay at cost of reduced accuracy. This paper focused on the fixed-polarity Reed-Muller(RM) functions area optimization by using approximate computing technique which is different from those used in traditional Boolean functions optimization in term of the characteristic of "XOR" in RM functions. The proposed algorithm mainly consists of the method of the error rate computing of RM functions using disjointed products and the approach of the approximate FPRM functions searching for less area under the given error rate constraint. The proposed algorithm is tested under MCNC (Microelectronics Center of North Carolina) benchmarks.The experimental results show that it can deal with the large function with 199 inputs. And by using the approximate computing technique

the average area can be reduced by 62.0% with the average error rate of 5.7%. The proposed approximate computing technique based algorithm is also beneficial for dynamic power saving and has little effect on the delay while optimizing the area of a circuit.