RAM is one of the most important macro-cells of FPGA,and RTL synthesis plays a critical role on the effective use of RAM resources in FPGA development.For the difficulty of multi-resources and multi-targets in RAM technology mapping of RTL synthesis,this paper presents a method of technology mapping for FPGA on-chip RAM.In this method,an unified technology-independent RAM model is proposed,and based on this model,RAM technology mapping is performed through a series of steps,including model set-up,mode-matching,cost calculation,and binding.When applied in RTL synthesis,this method is capable of mapping various styles of RAM RTL descriptions into the most appropriate type and number of FPGA on-chip RAM resources.Experimental result shows that this method achieves comparable RAM mapping results as the mainstream FPGA RTL synthesis tools-Synplify and XST,this technology has been integrated into the self-developed RTL synthesis-Hqsyn and has been applied into the FPGA market.
[1] Steven J E.Wilton.Heterogeneous technology mapping for area reduction in FPGA's with embedded memory arrays[A].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems[C].San Jose CA US:IEEE Trans,2000.19:56-68.
[2] M Milford,J McAllister.Valved dataflow for FPGA memory hierarchy synthesis[A].IEEE International Conference on Acoustics,Speech and Signal Processing[C].Kyoto Japan:IEEE Press,2012.1645-1648.
[3] Wang Yuxin,Zhang Peng,Cheng Xu,Jason Cong.An integrated and automated memory optimization flow for FPGA behavioral synthesis[A].Asia and SouthPacific Design Automation Conference-ASP-DAC[C].Sydney,Australia:IEEEPress,2012.257-262.
[4] T Kim,Liu C.Utilization of multiport memories for hierarchical data streams[A].ACM/IEEE Design Automation Conference[C].Dallas,Texas,US:IEEE Trans,1993.298-302.
[5] L Ramachandran,D Gajski,V Chaiyakul.An algorithm for array variable clustering[A].European Design and Test Conference[C].Paris France:EDAC,1994.262-266.
[6] P Marwedel,B Landwehr.Exploitarion of component information in a RAM-based architectural synthesis system[A].Logic and Architectural Synthesis,G.Saucier(Ed.)[D].Chapman & Hall Britain,1995.1-11.
[7] P Lippens,J Van Meerbergen,W Verhaegh,A Van Der Werf.Allocation of multiport memories for hierarchical data streams[A].Proceedings of the IEEE International Conference on Computer-Aided Design[C].Santa Clara,CA US:IEEE Trans,1993.728-735.
[8] F Balasa,F Catthoor,H De Man.Data-driven memory allocation for multi-dimensional signal processing systems[A].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems[C].San Jose CA US:IEEE Trans,1994.31-34.
[9] D Karchmer,J Rose.Definition and solution of the memory packing problem for field-programmable systems[A].IEEE/ACM International Conference On Computer-aided Design[C].San Jose CA US:IEEE Trans,1994.20-26.
[10] H Schmit,D Thomas.Array mapping in behavioral synthesis[A].Proceedings of the 8th international symposium on System synthesis[C].Cannes,France:ACM,1995.90-95.
[11] 周海峰,林争辉.RTL级综合中存储器工艺映射算法的研究[J].微电子报,2001,31(6):410-413. Zhou Haifeng,Lin Zhenghui.Memory mapping algorithms in synthesis[J].Microelectronics,2001,31(6):410-413.(in Chinese)
[12] S Bakshi,D Gajski.A memory selection algorithm for high-performance pipelines[A].Proceedings of the conference on European design automation[C].Los Alamitos,CA,US:IEEE Computer Society,1995.124-129.
[13] P K Jha,N D Dutt.Library mapping for memory[A].Proceedings of 1997 European Design and Test Conference[C].Washington,DC,US:IEEE Computer Society,1997.288.
[14] Xilinx,Inc.Datasheet:Virtex-II and Virtex-IIE FPGA Family[M].San Jose,CA,US,2008.
[15] Synopsis,Inc.Datasheet:Synplify Reference Manual[M].Mountain Veiw,CA,U.S.2012.
[16] Xilinx,Inc.Datasheet:XST Reference Manual[M].San Jose,CA,US,2008.
[17] Altera,Inc.User Guide:Internal Memory (RAM and ROM)[M].San Jose,CA,US,2013.
[18] Verilog hdl and VHDL opencores[M/OL].http://opencores.org/projects.2010-08.