一种功能可配置的可逆触发器设计

doi:10.12263/DZXB.20201291

电子学报 ›› 2022, Vol. 50 ›› Issue (6): 1466-1471.DOI: 10.12263/DZXB.20201291

一种功能可配置的可逆触发器设计

吴钰, 王伦耀, 储著飞, 夏银水

宁波大学信息科学与工程学院, 浙江宁波 315211

收稿日期:2020-11-17 修回日期:2021-03-16 出版日期:2022-06-25
- 作者简介:
- 吴钰女，1995年出生，安徽安庆人.硕士研究生.主要研究方向为可逆逻辑综合.E-mail: 13566361397@163.com
  王伦耀男，1972年出生，浙江宁波人.宁波大学信息科学与工程学院教授.主要研究方向为低功耗集成设计、集成电路设计自动化等.E-mail: wanglunyao@nbu.edu.cn
- 基金资助:
- 国家自然科学基金 (61471211); 浙江省自然科学基金 (LY19F040004); 宁波市自然科学基金 (2019A610077)

A Reversible Flip-flop Design with Configurable Function

WU Yu, WANG Lun-yao, CHU Zhu-fei, XIA Yin-shui

Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, Zhejiang 315211, China

Received:2020-11-17 Revised:2021-03-16 Online:2022-06-25 Published:2022-06-25
- Supported by:
- National Natural Science Foundation of China (61471211); National Natural Science Foundation of Zhejiang Province, China (LY19F040004); Ningbo Natural Science Fund (2019A610077)

摘要/Abstract

摘要：

不同于以往一种可逆触发器电路只能实现单一的D，T或JK触发器功能，本文在提出的3种触发器统一的次态方程基础上，设计了功能可配置的可逆单边沿和双边沿触发器.通过对输入变量的设置，提出的可逆触发器电路分别具有D，T或JK触发器逻辑功能，并能实现异步置数.提出的可逆触发器用Verilog硬件描述语言建模并用Modelsim软件仿真验证逻辑功能的正确性.相比于已有的单一功能可逆触发器，本文的可逆触发器在增加有限量子代价的基础上用单一电路实现3种不同触发器功能和异步置数.

关键词: 可逆逻辑, 可逆触发器, 可逆双边沿触发器, 可逆时序电路

Abstract:

Unlike the previous reversible flip-flops(RFFs) which have a single D, T or JK flip-flop characteristic function for one circuit, an edge-triggered(including dual edge-trigged) RFF with function configurable(FCRFF) is designed based on the proposed unified characteristic equation of D, T and JK FFs. By preset some inputs of FCRFF, the proposed edge-trigged FCRFF can act as D, T and JK reversible FF and also can load data asynchronously. The functions of proposed FCRFF are approved by simulation using Modelsim after modeled with Verilog HDL. Comparing with those published D, T and JK reversible FFs, the proposed FCRFF can combine D, T and JK reversible FFs' functions into one circuit and have asynchronous data loading function additionally only with a few quantum cost increasing.

Key words: reversible logic, reversible flip-flop, reversible dual edge-trigged flip-flop, reversible sequential circuit

中图分类号:

TP331.1

吴钰, 王伦耀, 储著飞, 等. 一种功能可配置的可逆触发器设计[J]. 电子学报, 2022, 50(6): 1466-1471.

Yu WU, Lun-yao WANG, Zhu-fei CHU, et al. A Reversible Flip-flop Design with Configurable Function[J]. Acta Electronica Sinica, 2022, 50(6): 1466-1471.

图/表 14

图1 Feynamn门

图2 Fredkin门

图3 可逆Latch电路结构

图4 功能可配置的可逆电平触发器

表1 C=1时图4电路Q_n取值情况

$Q I 1 I 2$	$Q_n (s = 1)$	$Q_n (s = 0)$
000	0	0
001	0	0
010	1	X*
011	X	1
100	1	0
101	0	1
110	1	X*
111	X	1

表1 C=1时图4电路Q_n取值情况

$Q I 1 I 2$	$Q_n (s = 1)$	$Q_n (s = 0)$
000	0	0
001	0	0
010	1	X*
011	X	1
100	1	0
101	0	1
110	1	X*
111	X	1

图5 功能可配置的可逆边沿触发器

图6 具有异步置数功能的可配置可逆边沿触发器

图7 功能可配置的可逆双边沿触发器

图8 具有异步置数功能的可逆双边沿触发器

图9 可逆边沿触发器仿真结果

图10 具有异步置数功能的可逆边沿JK触发器仿真结果

图11 可逆双边沿D触发器仿真结果

图12 具有异步置数功能的可逆双边沿JK触发器仿真结果

表2 与其他文献可逆触发器的QC值比较

单边沿触发器类型	文献[14]	本文	双边沿触发器类型	文献[14]	本文
D	13	18	D	19	24
T	14*		T	19*
JK	21*		JK	26*

参考文献 15

1	LANDAUERR. Irreversibility and heat generation in the computing process[J]. IBM Journal of Research and Development, 1961, 5(3): 183-191.
2	常丽, 朱宇祥, 蒋辉. 量子全加器设计[J]. 电子学报, 2019, 47(9): 1863-1867.
	CHANGL, ZHUY X, JIANGH. Design of quantum full adder[J]. Acta Electronica Sinica, 2019,47(9):1863-1867.(in Chinese)
3	NAVEENK B, PUNEETHG, SANDNGARAJUM N S. Low power Viterbi decoder design based on reversible logic gates[C]//International Conference on Electronics and Communication Systems. Coimbatore: IEEE, 2017: 201-205.
4	MONDALB, DEY K, CHAKRABORTYS. An efficient reversible cryptographic circuit design[C]//International Symposium on Vlsi Design and Test. Guwahati: IEEE, 2016: 1-6.
5	GOVINDAPRIYAK, PERIYASAMYM. Nano design of communication parts with QCA using reversible logic [C]//International Conference on Advanced Communication Control and Computing Technologies. Ramanathapuram: IEEE, 2017: 819-823.
6	管致锦, 秦小麟, 陶涛, 等. 可逆逻辑门网络的表示与级联[J]. 电子学报, 2010, 38(10): 2370-2376.
	GUANZ J, QINX L, TAOT, et al. Representation and cascade for reversible gate network[J]. Acta Electronica Sinica, 2010, 38(10): 2370-2376. (in Chinese)
7	KALANTARIZ, ESHGHIM, MOHAMMADIM, et al. Low-cost and compact design method for reversible sequential circuits[J]. The Journal of Supercomputing, 2019,75(11): 7497-7519 .
8	吴钰, 张莹, 王伦耀, 等. 一种可逆有限状态机的电路设计[J]. 电子学报, 2020, 48(11): 2226-2232.
	WUY, ZHANGY, WANGL Y, et al. Design of a reversible finite state machine[J]. Acta Electronica Sinica, 2020, 48(11): 2226-2232.(in Chinese)
9	ROHINIH, RAJASHEKARS, KUMARP. Design of basic sequential circuits using reversible logic[C]//2016 International Conference on Electrical, Electronics, and Optimization Techniques. Chennai: IEEE, 2016: 2110-2115.
10	ANDALOUSSII, SEDRAM B. A design of sequential reversible circuits by reversible gates[J]. International Journal of Engineering & Technology, 2020, 9(2): 397-402.
11	SLIMANIA, BENSLAMAA. Optimized 4-bit quantum reversible arithmetic logic unit[J]. International Journal of Theoretical Physics, 2017, 56(8): 2686-2696.
12	THAPLIYALH, RANGANATHANN. Design of reversible latches optimized for quantum cost, delay and garbage outputs[C]//2010 23rd International Conference on VLSI Design. Bangalore: IEEE, 2010: 235-240.
13	ANURADHAB, SIVAKUMARS. TOFFOLI based reversible sequential circuits[J]. International Journal of Advanced Information Science and Technology, 2014,23(23): 2319-2682.
14	MISRAN K, WAIRYAS, SEN B. Design of conservative, reversible sequential logic for cost efficient emerging nano circuits with enhanced testability[J]. Ain Shams Engineering Journal, 2018, 9(4): 2027-2037.
15	SINGHS, CHOUDHARYA, JAINM K. A brief overview of reversible logic gate and reversible circuits[J]. International Journal of Electronics Engineering, 2019, 11(2): 86-104.

[1]	吴钰, 张莹, 王伦耀, 储著飞, 夏银水. 一种可逆有限状态机的电路设计[J]. 电子学报, 2020, 48(11): 2226-2232.
[2]	常丽, 朱宇祥, 蒋辉. 量子全加器设计[J]. 电子学报, 2019, 47(9): 1863-1867.
[3]	王友仁, 沈先坤, 周影辉. 基于KFDD的可逆逻辑电路综合设计方法[J]. 电子学报, 2014, 42(5): 1025-1029.
[4]	徐明强, 管致锦, 张海豹. 基于最小混乱度的三值可逆逻辑综合算法[J]. 电子学报, 2013, 41(7): 1352-1357.
[5]	李志强, 陈汉武, 刘文杰, 薛希玲, 肖芳英. 基于新型量子逻辑门库的最优NCV三量子电路快速综合算法[J]. 电子学报, 2013, 41(4): 690-697.
[6]	朱皖宁, 陈汉武, 李志钢, 阮越, 王冬, 周刚. 基于NCP门库的一维量子行走可逆逻辑电路[J]. 电子学报, 2013, 41(1): 91-97.
[7]	杨忠明;陈汉武;王冬;. 基于二分法量子可逆逻辑电路综合[J]. 电子学报, 2012, 40(5): 1045-1049.
[8]	王友仁;黄媛媛;冯冉;张砦. 基于矩阵编码的量子可逆逻辑电路进化设计方法[J]. 电子学报, 2011, 39(11): 2576-2582.
[9]	王冬;陈汉武;安博;杨忠明. 基于矩阵初等变换的四量子比特可逆电路综合算法[J]. 电子学报, 2010, 38(11): 2561-2565.
[10]	管致锦;秦小麟;陶涛;施 . 可逆逻辑门网络的表示与级联[J]. 电子学报, 2010, 38(10): 2370-2376.
[11]	李志强;陈汉武;徐宝文;肖芳英;薛希玲. 四量子可逆逻辑电路快速综合算法[J]. 电子学报, 2008, 36(11): 2081-2089.

一种功能可配置的可逆触发器设计

A Reversible Flip-flop Design with Configurable Function

RichHTML

PDF

可视化

摘要/Abstract

引用本文

使用本文

图/表 14

参考文献 15

相关文章 11

编辑推荐

Metrics