电子学报 ›› 2022, Vol. 50 ›› Issue (7): 1548-1557.DOI: 10.12263/DZXB.20210448

• 学术论文 • 上一篇    下一篇

RTL级可扩展高性能数据压缩方法实现

陈晓杰1, 李斌2, 周清雷2   

  1. 1.数学工程与先进计算国家重点实验室,河南 郑州 450001
    2.郑州大学计算机与人工智能学院, 河南 郑州 450001
  • 收稿日期:2021-04-07 修回日期:2022-04-09 出版日期:2022-07-25 发布日期:2022-07-30
  • 作者简介:陈晓杰 男,1993年12月出生,河南武陟人.现为战略支援部队信息工程大学博士研究生,从事可重构计算、信息安全方面的有关研究.E-mail:cctvlibin@163.com
    李斌男,1986年12月出生,河南郑州人. 现为郑州大学计算机与人工智能学院讲师,主要从事可重构计算、信息安全方面的有关研究.E-mail:cctvlibin@163.com
    周清雷男,1962 年9 月出生,河南郑州人. 教授、博士生导师. 主要从事自动机理论、信息安全和计算复杂性理论方面的有关研究.
  • 基金资助:
    国家自然科学基金(61702518);国家重点研发计划重点专项(2018XXXXXXXX01)

Implementation of RTL Scalable High-Performance Data Compression Method

CHEN Xiao-jie1, LI Bin2, ZHOU Qing-lei2   

  1. 1.State Key Laboratory of Mathematical Engineering and Advanced Computing,Zhengzhou,Henan 450001,China
    2.School of Computer and Artificial Intelligence,Zhengzhou University,Zhengzhou,Henan 450001,China
  • Received:2021-04-07 Revised:2022-04-09 Online:2022-07-25 Published:2022-07-30

摘要:

针对传统的数据压缩实现方法处理性能较低,难以满足高速网络高负载、低能耗要求,本文提出了基于FPGA(Field-Programmable Gate Array)的高性能数据压缩方法.在数据计算方面,定制化一种专用并行数据匹配方法,并对压缩算法进行子任务划分,设计细粒度的串/并混合结构实现数据压缩和数据编码;在数据存储方面,设计了面向硬件的专用高效字典处理,并采用多级缓存机制优化访存结构;基于FPGA的资源面积,设计了多通道、可扩展数据压缩结构,并采用轮询策略实现多通道的数据分配和回收;在优化过程中,采用RTL(Register Transfer Level)实现数据压缩算法.实验结果表明优化后的压缩算法与CPU相比达到了1.634的加速比,吞吐量为4.33 Gb/s.

关键词: 数据压缩, FPGA, 多通道, 并行匹配, 多级缓存

Abstract:

As the low processing performance makes traditional data compression implementation methods difficult to meet the high load and low energy consumption requirements of high-speed networks, a high-performance data compression method based on field-programmable gate array is proposed. In terms of data calculation, this paper customize a dedicated parallel data matching method, divide the compression algorithm into sub-tasks, and design a fine-grained serial/parallel hybrid structure to achieve data compression and data encoding. In terms of data storage, a dedicated and efficient dictionary processing for hardware is designed, and a multi-level cache mechanism is used to optimize the memory access structure. Based on the resource area of FPGA, a multi-channel, scalable data compression structure is designed, and a polling strategy is used to realize multi-channel data allocation and recovery. In the optimization process, register transfer level is used to realize the data compression algorithm. The experimental results show that the optimized compression algorithm achieves a speedup ratio of 1.634 compared with the CPU, with a throughput of 4.33 Gb/s.

Key words: data compression, field-programmable gate array, multi-channel, parallel matching, multi-level cache

中图分类号: