电子学报 ›› 2022, Vol. 50 ›› Issue (5): 1243-1254.DOI: 10.12263/DZXB.20210637
所属专题: 长摘要论文
田春生1,2, 陈雷2, 王源1, 王硕2, 周婧2, 张瑶伟2, 庞永江2, 周冲2, 马筱婧2, 杜忠2, 薛钰2
收稿日期:
2021-05-18
修回日期:
2021-08-24
出版日期:
2022-05-25
通讯作者:
作者简介:
基金资助:
TIAN Chun-sheng1,2, CHEN Lei2, WANG Yuan1, WANG Shuo2, ZHOU Jing2, ZHANG Yao-wei2, PANG Yong-jing2, ZHOU Chong2, MA Xiao-jing2, DU Zhong2, XUE Yu2
Received:
2021-05-18
Revised:
2021-08-24
Online:
2022-05-25
Published:
2022-06-18
Corresponding author:
Supported by:
摘要:
随着大规模集成电路器件复杂度与容量的不断提升,现场可编程门阵列(Field Programmable Gate Array, FPGA)以高度的并行、可定制和可重构的特性得到了广泛的关注与应用. 在制约FPGA发展的众多因素中,最为关键的便是电子设计自动化(Electronic Design Automation, EDA)技术,作为FPGA EDA流程中的关键环节,布局和布线技术的研究对于FPGA的重要性不言而喻. 本文综述了面向FPGA的布局和布线技术,包括基于划分的布局、基于启发式的布局、基于解析式的布局、FPGA串行布线和FPGA并行布线等技术,分析对比了不同技术方法的优缺点,在此基础上,本文还展望了未来FPGA布局和布线技术的发展趋势,将为FPGA未来健康可持续的发展提供有力支撑.
中图分类号:
田春生, 陈雷, 王源, 等. 面向FPGA的布局与布线技术研究综述[J]. 电子学报, 2022, 50(5): 1243-1254.
Chun-sheng TIAN, Lei CHEN, Yuan WANG, et al. Review on Technology of Placement and Routing for the FPGA[J]. Acta Electronica Sinica, 2022, 50(5): 1243-1254.
布局技术 | 优势 | 不足 |
---|---|---|
基于划分的布局技术 | 将复杂的电路设计分割为较简单的电路设计,能够快速对局部电路进行处理,收敛速度快 | 布局质量上存在劣势,容易陷入局部最优解 |
基于启发式的布局技术 | 相对于最优算法而提出,在时间允许的情况下,能够获得布局的最优解 | 运行时间长,布局收敛速度慢 |
基于解析式的布局技术 | 完全依赖于数学方法,最终的布局质量能够通过数学分析来证明,具有较高的布局质量,收敛较快 | 较高的数学功底以抽象FPGA布局问题,不同的FPGA抽象形式不同,不能通用 |
表1 FPGA布局技术总结
布局技术 | 优势 | 不足 |
---|---|---|
基于划分的布局技术 | 将复杂的电路设计分割为较简单的电路设计,能够快速对局部电路进行处理,收敛速度快 | 布局质量上存在劣势,容易陷入局部最优解 |
基于启发式的布局技术 | 相对于最优算法而提出,在时间允许的情况下,能够获得布局的最优解 | 运行时间长,布局收敛速度慢 |
基于解析式的布局技术 | 完全依赖于数学方法,最终的布局质量能够通过数学分析来证明,具有较高的布局质量,收敛较快 | 较高的数学功底以抽象FPGA布局问题,不同的FPGA抽象形式不同,不能通用 |
分类 | Benchmarks | 串行对比基准 | 并行模型 | 同步方法 | 确定性 | 可扩展性 | 文献 | |
---|---|---|---|---|---|---|---|---|
粗粒度 | 字典序法 | alu4, s1A | PathFinder | 分布式内存 | 消息传递 | 不具备 | 扩展性低 | [ |
负载均衡法 | MCNC, VPR 5.0 | VPR 5.0 | 分布式内存 | 消息传递 | 具备 | 扩展性低 | [ | |
迭代划分法 | VPR 7.0 | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | |
VPR 7.0 | VPR 7.0 | 分布式内存 | 消息传递 | 具备 | 扩展性低 | [ | ||
VPR 7.0 | VPR 7.0 | 分布式内存 | 消息传递 | 具备 | 扩展性高 | [ | ||
VPR 7.0, Titan | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
细粒度 | Posix线程 | VPR 8.0 | VPR 8.0 | 共享式内存 | 消息传递 | 具备 | 扩展性高 | [ |
MCNC, VPR5.0 | VPR5.0 | 分布式内存 | 同步路障 | 具备 | 扩展性低 | [ | ||
VPR 7.0 | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
VPR 7.0 | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
Galois模型 | IWLS | VPR 5.0 | 共享式内存 | 同步锁 | 不具备 | 扩展性高 | [ | |
IWLS | VPR 5.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
混合粒度 | / | Titan | VPR 7.0 | 共享式内存 | 同步锁 | 不具备 | 扩展性高 | [ |
MCNC | VPR 5.0 | 共享式内存 | 同步路障 | 具备 | 扩展性低 | [ |
表2 FPGA并行布线技术
分类 | Benchmarks | 串行对比基准 | 并行模型 | 同步方法 | 确定性 | 可扩展性 | 文献 | |
---|---|---|---|---|---|---|---|---|
粗粒度 | 字典序法 | alu4, s1A | PathFinder | 分布式内存 | 消息传递 | 不具备 | 扩展性低 | [ |
负载均衡法 | MCNC, VPR 5.0 | VPR 5.0 | 分布式内存 | 消息传递 | 具备 | 扩展性低 | [ | |
迭代划分法 | VPR 7.0 | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | |
VPR 7.0 | VPR 7.0 | 分布式内存 | 消息传递 | 具备 | 扩展性低 | [ | ||
VPR 7.0 | VPR 7.0 | 分布式内存 | 消息传递 | 具备 | 扩展性高 | [ | ||
VPR 7.0, Titan | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
细粒度 | Posix线程 | VPR 8.0 | VPR 8.0 | 共享式内存 | 消息传递 | 具备 | 扩展性高 | [ |
MCNC, VPR5.0 | VPR5.0 | 分布式内存 | 同步路障 | 具备 | 扩展性低 | [ | ||
VPR 7.0 | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
VPR 7.0 | VPR 7.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
Galois模型 | IWLS | VPR 5.0 | 共享式内存 | 同步锁 | 不具备 | 扩展性高 | [ | |
IWLS | VPR 5.0 | 共享式内存 | 同步锁 | 具备 | 扩展性高 | [ | ||
混合粒度 | / | Titan | VPR 7.0 | 共享式内存 | 同步锁 | 不具备 | 扩展性高 | [ |
MCNC | VPR 5.0 | 共享式内存 | 同步路障 | 具备 | 扩展性低 | [ |
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