1 |
LENT C S, TOUGAW P D. A device architecture for computing with quantum dots[J]. Proceedings of the IEEE, 1997, 85(4): 541-557.
|
2 |
ZHANG Y Q, XIE G J, SUN M B, et al. Design of normalised and simplified FAs in quantum-dot cellular automata[J]. The Journal of Engineering, 2017, 2017(10): 557-565.
|
3 |
CHO H, SWARTZLANDER E E. Adder and multiplier design in quantum-dot cellular automata[J]. IEEE Transactions on Computers, 2009, 58(6): 721-727.
|
4 |
ABUTALEB M M. A novel configurable flip flop design using inherent capabilities of quantum-dot cellular automata[J]. Microprocessors and Microsystems, 2018, 56: 101-112.
|
5 |
SABBAGHI-NADOOSHAN R, KIANPOUR M. A novel QCA implementation of MUX-based universal shift register[J].Journal of Computational Electronics, 2014, 13(1): 198-210.
|
6 |
TOUGAW D, JOHNSON E W, EGLEY D. Programmable logic implemented using quantum-dot cellular automata[J]. IEEE Transactions on Nanotechnology, 2012, 11(4): 739-745.
|
7 |
SANDHU A, GUPTA S. A majority gate based RAM cell design with least feature size in QCA[J]. Gazi University Journal of Science, 2019, 32(4): 1150-1165.
|
8 |
NIEMIER M T, KOGGE P M. Problems in designing with QCAs: Layout = timing[J]. International Journal of Circuit Theory and Applications, 2001, 29(1): 49-62.
|
9 |
VANKAMAMIDI V, OTTAVI M, LOMBARDI F. Two-dimensional schemes for clocking/timing of QCA circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(1): 34-44.
|
10 |
CAMPOS C A T, MARCIANO A L, VILELA NETO O P, et al. USE: A universal, scalable, and efficient clocking scheme for QCA[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(3): 513-517.
|
11 |
GOSWAMI M, MONDAL A, MAHALAT M H, et al. An efficient clocking scheme for quantum-dot cellular automata[J]. International Journal of Electronics Letters, 2020, 8(1): 83-96.
|
12 |
DENG F F, XIE G J, CHENG X, et al. CFE: A convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata[J]. IET Circuits, Devices & Systems, 2020, 14(1): 88-92.
|
13 |
WALTER M, WILLE R, TORRES F S, et al. Fiction: An open source framework for the design of field-coupled nanocomputing circuits[EB/OL]. [2021-09-01]. .
|
14 |
FORMIGONI R E, FERREIRA R S, NACIF J A M. Ropper: A placement and routing framework for field-coupled nanotechnologies[C]//2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI). Piscataway: IEEE, 2019: 1-6.
|
15 |
NGUYEN J, RAVICHANDRAN R, LIM S K, et al. Global placement for quantum-dot cellular automata based circuits[J]. Georgia Institute of Technology, 2003: 1-17.
|
16 |
ANTONELLI D A, CHEN D Z, DYSART T J, et al. Quantum-Dot Cellular Automata (QCA) circuit partitioning: Problem modeling and solutions[C]//Proceedings of the 41st Annual Design Automation Conference. San Diego: IEEE, 2004: 363-368.
|
17 |
RAVICHANDRAN R, LIM S K, NIEMIER M. Automatic cell placement for quantum-dot cellular automata[J]. Integration, 2005, 38(3): 541-548.
|
18 |
WALTER M, WILLE R, GROßE D, et al. An exact method for design exploration of quantum-dot cellular automata[C]//2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). Piscataway: IEEE, 2018: 503-508.
|
19 |
WALTER M, WILLE R, TORRES F S, et al. Scalable design for field-coupled nanocomputing circuits[C]//Proceedings of the 24th Asia and South Pacific Design Automation Conference. Tokyo: ACM, 2019: 197-202.
|
20 |
WALTER M, HAASWIJK W, WILLE R, et al. One-pass synthesis for field-coupled nanocomputing technologies [C]//Proceedings of the 26th Asia and South Pacific Design Automation Conference. Tokyo: ACM, 2021: 574-580.
|
21 |
TRINDADE A, FERREIRA R, NACIF J A M, et al. A placement and routing algorithm for quantum-dot cellular automata[C]//Proceedings of the 2016 29th Symposium on Integrated Circuits and Systems Design. Belo Horizonte: IEEE, 2016: 1-6.
|
22 |
FONTES G, SILVA P A R L, NACIF J A M, et al. Placement and routing by overlapping and merging QCA gates[C]//2018 IEEE International Symposium on Circuits and Systems. Piscataway: IEEE, 2018: 1-5.
|
23 |
AMARU L, GAILLARDON P E, MICHELI G D. The EPFL combinational benchmark suite[C]//Proceedings of the 24th International Workshop on Logic & Synthesis, Mountain View: EPFL, 2015: 1-5.
|