电子学报

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高吞吐率流水线结构的ZUC-256流密码硬件设计

刘云涛1,2, 申泽生1, 方硕1,2, 王云3   

  1. 1.哈尔滨工程大学信息与通信工程学院,黑龙江 哈尔滨 150001
    2.先进船舶通信与信息技术工业和信息化部重点实验室,黑龙江 哈尔滨 150001
    3.广东省大湾区集成电路与系统应用研究院,广东 广州 510535
  • 收稿日期:2021-09-28 修回日期:2022-05-01 出版日期:2023-02-02
    • 作者简介:
    • 刘云涛 男,1980年出生,黑龙江鹤岗人.工学博士,副教授,博士生导师.主要研究方向为模拟/数模混合集成电路设计、CMOS图像传感器.E-mail: lyt@hrbeu.edu.cn
      申泽生 男,1997年出生,山东泰安人.硕士.主要研究方向为数字集成电路设计、硬件加密算法、数字信号处理.E-mail: fateszs@163.com
    • 基金资助:
    • 黑龙江省自然科学基金面上项目(JJ2018ZR1021);中央高校基本科研业务费专项资金(3072021CF0806)

A Hardware Design of ZUC-256 Stream Cipher of Pipelining Structure with High Throughput

LIU Yun-tao1,2, SHEN Ze-sheng1, FANG Shuo1,2, WANG Yun3   

  1. 1.College of Information and Communication Engineering,Harbin Engineering University,Harbin,Heilongjiang 150001,China
    2.Key Laboratory of Advanced Marine Communication and Information Technology,Ministry of Industry and;Information Technology,Harbin,Heilongjiang 150001,China
    3.Guangdong Greater Area Institute of Integrated Circuit and System,Guangzhou,Guangdong 510535,China
  • Received:2021-09-28 Revised:2022-05-01 Online:2023-02-02
    • Supported by:
    • National Natural Science Foundation of Heilongjiang Province(JJ2018ZR1021);Fundamental Research Funds for the Central Universities(3072021CF0806)

摘要:

ZUC-256是为提供5G应用环境256 bit安全性而设计的流密码算法,数据处理速率是其核心性能之一,为此本文提出一种具有高吞吐率特性的硬件设计方案.该方案采用流水线拆分关键路径初步提升系统工作频率,并提出一种完成模(231-1)加算法的优化电路进一步缩短关键路径延迟,该模加结构相较于现有结构缩短了42%的逻辑延迟,能够显著提升系统工作频率和吞吐率.本研究分别采用Xilinx公司的Virtex-5器件、Alter公司的DE2-115器件和TSMC 90 nm工艺实现了该流密码硬件结构.实验测试结果表明,采用TSMC 90 nm工艺实现的ASIC系统工作频率达到最高1200 MHz,吞吐率可达38.4 Gbps,比现有研究成果提升71%.

关键词: 5G, 祖冲之算法, 知识产权核, 高吞吐率, 流水线

Abstract:

ZUC-256 is a stream cipher algorithm designed to provide 256-bit security in a 5G application environment. The data processing rate is one of ZUC-256 core performances. Therefore, a hardware design scheme with high throughput characteristics is proposed. This scheme uses pipeline to split the critical path to increase the operating frequency of the system, and proposes an optimized circuit that completes the modular(231-1) addition algorithm to further shorten the critical path delay. Compared with the conventional structure, the modular addition structure can shorten the path delay by 42%, which can significantly improve the working frequency and throughput rate of the system. This research implemented the structure based on Xilinx's Virtex-5 device, Alter's DE2-115 device and TSMC 90 nm technology respectively. The experimental results shows that the ASCI system implemented by TSMC 90 nm technology achieves the maximum operating frequency of 1200 MHz, and the throughput rate can reach 38.4 Gbps, which is 71% higher than the existing research results.

Key words: 5G, ZUC-256, IP core, throughput rate, pipe-line

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