绝缘体上硅功率半导体单芯片集成技术

doi:10.12263/DZXB.20220492

电子学报

• •

绝缘体上硅功率半导体单芯片集成技术

张龙¹, 刘斯扬¹, 孙伟锋¹, 马杰¹, 盘成务¹, 何乃龙², 张森², 苏巍²

^1.东南大学国家ASIC工程研究中心，江苏南京 210096
^2.华润上华科技有限公司，江苏无锡 214061

收稿日期:2022-05-05 修回日期:2022-11-07 出版日期:2022-11-26
- 通讯作者:
- 孙伟锋
- 作者简介:
- 张龙男，1986年出生，江苏徐州人.2010年于中国矿业大学获学士学位，2013年于东南大学获硕士学位，2018年于东南大学获博士学位，2018至2020年于东南大学从事博士后工作，2020年至今为东南大学教师，副高级职称，博士生导师.主要研究方向为功率半导体集成工艺及器件.E-mail: longzh@seu.edu.cn
  刘斯扬男，1987年出生，安徽合肥人.2008年于合肥工业大学获学士学位，2011年于东南大学获硕士学位，2015年于东南大学获博士学位，2015至2017年于东南大学从事博士后工作，目前为东南大学青年首席教授，国家高层次人才，博士生导师.主要研究方向为功率半导体集成工艺及器件.E-mail: liusy2017@seu.edu.cn
  孙伟锋（通讯作者）男，1977年出生，江苏武进人.2000年、2003年、2007年于东南大学分别获得学士、硕士及博士学位，目前为东南大学首席教授，国家高层次人才，江苏特聘教授，博士生导师.主要研究方向为功率集成电路. Email: swffrog@seu.edu.cn
- 基金资助:
- 国家自然科学基金 (62274032); 江苏省科技成果项目 (BA2022005)

Study on the Silicon-on-Insulator Power Semiconductor Monolithic Integration Technology

ZHANG Long¹, LIU Si-yang¹, SUN Wei-feng¹, MA Jie¹, PAN Cheng-wu¹, HE Nai-long², ZHANG Sen², SU Wei²

^1.National ASIC System Engineering Research Center，Southeast University，Nanjing，Jiangsu 210096，China
^2.CSMC Technologies Co. ，Wuxi，Jiangsu 214061，China

Received:2022-05-05 Revised:2022-11-07 Online:2022-11-26
- Corresponding author:
- SUN Wei-feng

摘要/Abstract

摘要：

利用单芯片集成技术制造的智能功率芯片具有体积小、寄生小、损耗低等方面的优势，其技术难度远高于传统的多芯片、单封装形式的智能功率模块.本文首先介绍了单片智能功率芯片的架构与技术需求.然后，探讨了绝缘体上硅功率半导体单芯片集成的工艺流程和器件类型.接着，总结了高压横向IGBT器件技术、续流二极管器件技术、LDMOS器件技术的特征和效果.此外，还讨论了单片智能功率芯片的相关可靠性问题，包括高压互连线效应和低温雪崩不稳定.本课题组在功率半导体集成型器件的电流能力、关断速度、短路承受能力、反向恢复峰值电流、安全工作区、高压互连线屏蔽、低温可靠性等关键特性优化或可靠性提升方面进行了自主创新，构建了基于绝缘体上硅的功率半导体单芯片集成技术，并成功研制了单片智能功率芯片.

关键词: 功率半导体, 绝缘体上硅, 单片集成, 功率集成电路, 功率器件

Abstract:

The intelligent power chip designed and manufactured based on the single-chip integration technology has the advantages of small size, small parasitic element and low loss. Its technical difficulty is much higher than the intelligent power module with multiple co-packaged chips. Firstly, this paper introduces the block diagram of the single-chip intelligent power chip and its technical requirements. Then, the process flow and device types of the silicon-on-insulator(SOI) power semiconductor single-chip integration technology are discussed. Then, the features and technical effect of the high-voltage lateral IGBT, freewheeling diode and LDMOS technologies are summarized. Additionally, the reliability of single-chip intelligent power chip is discussed, including high-voltage interconnection effect and low-temperature instability. The research group of this paper has made independent innovation in the optimization or reliability improvement of key characteristics of integrated power semiconductor devices, such as current capability, turn-off speed, short-circuit withstand capability, reverse recovery peak current, safe operation area, high-voltage interconnection shielding, low-temperature reliability and so on. We developed the power semiconductor single-chip integration technology based on SOI, and realized the localization of single-chip intelligent power chip.

Key words: power semiconductor, silicon-on-insulator, single-chip integration, power integrated circuit, power device

中图分类号:

TN433

张龙, 刘斯扬, 孙伟锋, 马杰, 盘成务, 何乃龙, 张森, 苏巍. 绝缘体上硅功率半导体单芯片集成技术[J]. 电子学报, DOI: 10.12263/DZXB.20220492.

ZHANG Long, LIU Si-yang, SUN Wei-feng, MA Jie, PAN Cheng-wu, HE Nai-long, ZHANG Sen, SU Wei. Study on the Silicon-on-Insulator Power Semiconductor Monolithic Integration Technology[J]. Acta Electronica Sinica, DOI: 10.12263/DZXB.20220492.

图/表 33

图1 传统智能功率模块(IPM)的内部架构示意图

图2 本课题组所研发的国产单片智能功率芯片照片

图3 单片智能功率芯片的架构

图4 SOI全集成工艺剖面结构示意图(图中未显示被动元件)

图5 SOI全集成工艺关键步骤

图6 多沟道器件结构示意图

图7 U型沟道结构示意图

图8 传统结构和U型沟道结构的I-V曲线对比(WPC、WOC、WPE及α见图7标注)

图9 各类技术的击穿电压与特征导通电阻折中关系

图10 沟槽栅U型沟道器件结构示意图

图11 具有漂移区双沟槽的LIGBT器件结构示意图

图12 传统结构与双沟槽结构耐压时的表面电势分布对比图

图13 传统结构和双沟槽结构的感性负载关断曲线(ST、L1、L2见图11标注)

图14 三沟槽结构示意图

图15 三沟槽结构的形成过程示意图

图16 三沟槽及其他SOI-LIGBT器件的电流密度(JC)与关断时间(tOFF)折中关系

图17 复合集电极结构示意图

图18 "W"型缓冲层的形成方法

图19 复合集电极结构的等效电路图(R1代表漂移区的寄生电阻;R2代表P型体区中的寄生电阻)

图20 复合集电极器件和传统器件载流子分布对比

图21 复合集电极器件和传统器件的关断特性曲线对比

图22 复合集电极器件和传统器件的短路特性曲线对比

图23 所研发的LDMOS器件的版图示意图

图24 所研发的LDMOS器件在200 ℃时的连续脉冲工作波形(无负载的反复短路状态)

图25 SOI基高压FWD结构示意图

图26 所研发的FWD的反向恢复特性波形

图27 双沟槽高压互连线屏蔽结构

图28 沟槽刻蚀后的SEM图

图29 双沟槽高压互连线结构击穿电压测试曲线

表1 本课题组提出的双沟槽高压互连线屏蔽技术与其他技术的对比

参数	本课题组技术	厚介质技术^[71]	淡P阱技术^[71]	多浮空场板技术^[71]
带高压互连线结构的击穿电压(V)	550	539	716	732
不带高压互连线结构的击穿电压(V)	550	876	876	876
ƞ_s	100%	62%	82%	84%

图30 不同温度下的VCE随时间变化曲线

图31 雪崩击穿时的电荷积累示意图

图32 采用N型衬底器件的雪崩稳定性测试结果

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绝缘体上硅功率半导体单芯片集成技术

Study on the Silicon-on-Insulator Power Semiconductor Monolithic Integration Technology

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