电子学报 ›› 2014, Vol. 42 ›› Issue (3): 583-586.DOI: 10.3969/j.iss.0372-2012-2014.03.024

• 科研通信 • 上一篇    下一篇

基于比特重排的减少机顶盒芯片DDR接口SSN的方法

梁骏1, 叶剑兵2, 王洪海2, 张明1   

  1. 1. 浙江大学信息与通信工程研究所, 浙江杭州 310027;
    2. 杭州国芯科技股份有限公司, 浙江杭州 310027
  • 收稿日期:2012-12-28 修回日期:2013-07-09 出版日期:2014-03-25
    • 作者简介:
    • 梁骏 男,1978年7月出生于浙江省临海市.现为浙江大学信息与通信工程研究所博士研究生.主要研究方向为高速电路设计、芯片可测试设计、系统芯片设计与验证等.E-mail:justin.w.liang@gmail.com
    • 基金资助:
    • 国家自然科学基金 (No.61072081,No.61271338); 国家科技重大专项 (No.2009ZX01033-001-007)

A Bit-Rearrangement Based Method to Reduce SSN of DDR Interface in STB Chip Design

LIANG Jun1, YE Jian-bing2, WANG Hong-hai2, ZHANG Ming1   

  1. 1. Institute of Information and Communication Engineering, Zhejiang University, Hangzhou, Zhejiang 310027, China;
    2. Hangzhou Nationalchip S&T Co., Ltd, Hangzhou, Zhejiang 310027, China
  • Received:2012-12-28 Revised:2013-07-09 Online:2014-03-25 Published:2014-03-25
    • Supported by:
    • National Natural Science Foundation of China (No.61072081, No.61271338); National Science and Technology Major Project of the Ministry of Science and Technology (No.2009ZX01033-001-007)

摘要: 封装电感引起的SSN(Simultaneous Switching Noise,同步开关噪音)效应阻碍低成本QFP(Quad Flat Package,四方型扁平式封装)封装的机顶盒芯片的DDR SDRAM(Double Data Rate Static Random Access Memory,双速率静态随机访问存储器,DDR)接口的传输频率.本文利用视频数据的相关性,及DDR颗粒的数据比特可以任意交换的特点,提出对DDR接口数据进行数据比特重排的方法来降低SSN效应.视频解码器使用到的数据在二维空间上高度相关.在DDR接口版图设计时将高比特位的数据与低比特位的数据在空间上交错放置,可使得DDR接口的电流分布更加平衡,减少通过封装寄生电感的平均电流,最终减少SSN.本文提出的方法成功用于台积电55nm工艺高清机顶盒芯片的设计.QFP封装的样片的DDR接口传输速率达到1066Mbps.

关键词: DDR SDRAM(双速率静态随机访问存储器), SSN(同步开关噪音), QFP(四方型扁平式封装), 比特重排

Abstract: The SSN (Simultaneous Switching Noise) caused by parasitic inductance of low cost QFP (Quad Flat Package) package limits the DDR (Double Date Rate) interface data transfer rate of STB (Set Top Box) chip.This paper discusses the video data interdependency and DDR bus bit interchangeability,and proposes a bit-rearrangement method to reduce SSN of DDR interface.The video data used in STB chip has strong correlation in two space dimensions.Logic bits of DDR bus are physically interlaced according to specific algorithm during layout design phase,which makes spatial distribution of DDR output drive current more balanced.The balanced distribution decreases average current running through each pair of power/ground pin and reduces SSN accordingly.This method is applied in a HDTV (High Definition TeleVision) chip on TSMC(Taiwan Semiconductor Manufacturing Company) 55nm process.The DDR data transfer rate of the test chip in QFP package attains 1066Mbps.

Key words: DDR SDRAM (Double Data Rate Static Random Access Memory), SSN (Simultaneous Switching Noise), QFP (Quad Flat Package), bit rearrangement

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