电子学报 ›› 2012, Vol. 40 ›› Issue (5): 949-954.DOI: 10.3969/j.issn.0372-2112.2012.05.014

• 学术论文 • 上一篇    下一篇

一种改进的层次化SOCs并行测试封装扫描单元

邓立宝, 乔立岩, 俞洋, 彭喜元   

  1. 哈尔滨工业大学自动化测试与控制系, 黑龙江哈尔滨 150080
  • 收稿日期:2011-03-25 修回日期:2012-01-10 出版日期:2012-05-25 发布日期:2012-05-25

A Modified Parallel Wrapper Cell for Hierarchical SOCs Test

DENG Li-bao, QIAO Li-yan, YU Yang, PENG Xi-yuan   

  1. Department of Automatic Test and Control, Harbin Institute of Technology, Harbin, Heilongjiang 150080, China
  • Received:2011-03-25 Revised:2012-01-10 Online:2012-05-25 Published:2012-05-25

摘要: 测试封装是实现SOC内部IP核可测性和可控性的关键,而扫描单元是测试封装最重要的组成部分.然而传统的测试封装扫描单元在应用于层次化SOCs测试时存在很多缺点,无法保证内部IP核的完全并行测试,并且在测试的安全性,功耗等方面表现出很大问题.本文提出一种改进的层次化SOCs测试封装扫描单元结构,能够有效解决上述问题,该结构的主要思想是对现有的扫描单元进行改进,实现并行测试的同时,通过在适当的位置增加一个传输门,阻止无序的数据在非测试时段进入IP核,使得IP核处于休眠状态,保证了测试的安全性,实现了测试时的低功耗.最后将这种方法应用在一个工业上的层次化SOCs,实验分析表明,改进的测试封装扫描单元比现有扫描单元在增加较小硬件开销的前提下,在并行测试、低功耗、测试安全性和测试覆盖率方面有着明显的优势.

关键词: 层次化SOCs, 测试封装扫描单元, 并行测试, 低功耗

Abstract: Test wrapper,which to make IP cores in SOC measurable and controllable,is the key architecture,and its important part is wrapper cell. Traditional test wrapper has many shortcomings,such as parallel test,test secure and test power,when used in hierarchical SOCs. This paper presented a modified test wrapper design for embedded IP cores,which only inserted a CMOS transmission gate to the test wrapper cell to eliminate the precarious effect to IP cores,to make the IP cores dormancy. Experiments on an industry hierarchical SOCs show that the proposed test wrapper cell not only takes less area overhead and time delay,but also make test parallel,secure and fully,thus decreases the dynamic test power during scan shifting.

Key words: hierarchical SOCs, wrapper cell, parallel test, low power

中图分类号: