关键词: 三维芯片, 布图规划, 过硅通孔, 热量, 互连线功耗

Abstract: Three-dimensional (3D) chip is structured by vertically stacked multi-planar device layers,which is used by TSVs (Through Silicon Vias) for vertical interconnection between different layers,so it significantly reduces the wire length and increases chip integration density.However,Series of problems are brought by three-dimensional chips.for example,a single TSV occupies a relatively larger chip area in terms of the present feature size,and the immaturity of the alignment technique of the TSVs also lowers the yield of the chip,so the introduction of too many TSVs will increase the cost of chip manufacturing and testing.Vertical stacking makes the chip integration density and the power density in the same area increase a lot simultaneously,resulting heat doubles.For these problems,we propose a collaborative considered TSV and Thermal Floorplanning (2TF) algorithm,that the device power,interconnect power and the number of TSVs are simultaneously considered.The experimental results on the MCNC benchmark circuits have shown that the number of TSVs and the peak temperature of the chip have a greater improvement.

Key words: three-dimensional chip, floorplaning, through silicon via, thermal, interconnect power