[1] Y Dou,Y Lei,G Wu,et al.FPGA accelerating double/quad-double high precision floating-point application for exascale computing. Proceedings of 24th International Conference on Supercomputing. Tsukuba:ACM Press,2010.325-336. [2] D H Bailey.High-precision floating-point arithmetic in scientific computation[J].Computing in Science and Engineering,2005,7(3):54-61. [3] ANSI/IEEE Std 754-2008, Standard for Binary Floating Point Arithmetic ANSI/IEEE Standard 754-2008[S]. [4] L Fousse,G Hanrot,V Lefevre,P Pelissier.MPFR:A multiple-precision binary floating-point library with correct rounding[J].Transactions on Mathematical Software,2007,33(2):1-15. [5] Y Hida,X S Li,D H Bailey.Quad-Double Arithmetic:Algorithms,Implementation,and Application. Berkeley:Lawrence Berkeley National Laboratory,2000. [6] E M Schwarz,R M Smth,C A Krygowski.The S/390 G5 floating point unit supporting hex and binary architectures. Proceedings of the 14th IEEE Symposium on Computer Arithmetic. Adelaide:IEEE Press,1999.836-841. [7] A Akkas.Dual-mode quadruple precision floating-point adder. Proceedings of 9th Euromicro Conference on Digital System Design. Dubrovnik:IEEE Press,2006.211-220. [8] A Akkas,M Schult.Dual-mode floating-point multiplier architectures with parallel operations[J].Journal of Systems Architecture,2006,52(10):549-562. [9] A Isseven,A Akkas.A dual-mode quadruple precision floating-point divider. Proceedings of Fortieth Asilomar Conference on Signals,Systems and Computers. Pacific Grove:IEEE Press,2006.1697-1701. [10] Ej-Araby,E Gonzalez,I El-Ghazawi.Bringing high performance reconfigurable computing to exact computations. Proceedings of International Conference on Field Programmable Logic and Applications. Amsterdam:IEEE Press,2007.79-85. [11] J Detrey,F Dinechin,X Pujol.Return of the hardware floating-point elementary function. Proceedings of the 18th IEEE Symposium on Computer Arithmetic. Montepellier:IEEE Press,2007.161-168. [12] K K Parhi,H R Srinivas.A fast radix-4 division algorithm and its architecture. IEEE Transactions on Computers,1995,44(6):826-831. [13] Y Li,W Chu.Parallel-array implementations of a non-restoring square root algorithm. IEEE International Conference on Computer Design. Austin:IEEE Press,1997.690-695. [14] J S Walther.A unified algorithm for elementary functions. Proceedings of AFIPS Joint Computer Conference. New York:IEEE Press,1971.379-385. [15] P Soderquist,M Leeser.Division and square root:Choosing the right implementation[J].IEEE Micro,1997,17(4):56-66. [16] M D Ercegovac,L Imbert,et al.Improving goldschmidt division,square root and square root reciprocal[J].IEEE Transactions on Computers,2000,49(7):759-763. [17] J Zhou,Y Dou,Y Lei,et al.Double precision Hybrid mode floating-point FPGA CORDIC co-processor. Proceedings of the 10th IEEE International Conference on High Computing and Communications. Dalin:IEEE Press,2008.182-189. |