三维片上网络故障及拥塞感知的容错路由器设计

doi:10.3969/j.issn.0372-2112.2013.05.013

PDF(3068 KB)

电子学报 ›› 2013, Vol. 41 ›› Issue (5) : 912-917. DOI: 10.3969/j.issn.0372-2112.2013.05.013

学术论文

三维片上网络故障及拥塞感知的容错路由器设计

欧阳一鸣¹, 张一栋¹, 梁华国², 黄正峰²

作者信息 +

A Fault-Tolerant Design of Faults and Congestion-Aware Router in Three-Dimensional Network-on-Chip

OUYANG Yi-ming¹, ZHANG Yi-dong¹, LIANG Hua-guo², HUANG Zheng-feng²

Author information +

文章历史 +

摘要

三维片上网络中路由器的输入端口和交叉开关出现故障,将严重影响整个网络的性能,因此文章提出了一种故障及拥塞感知的容错路由器.通过增加一个冗余的输入端口和旁路总线,不仅能实现对输入端口和交叉开关容错的目的,而且还能在没有端口故障的情况下使用冗余端口有效地解决拥塞问题.实验表明此容错机制能够使得网络在故障路由器多、拥塞严重的情况下,仍然保持良好的性能.

Abstract

The faults occurring in the input ports and crossbar of the router will seriously affect the performance of the entire network in Three-dimensional Network-on-Chip.This article proposes a fault and congestion-aware fault-tolerant router.By adding a redundancy of the input port and the bypass bus,our scheme can achieve fault tolerance of input ports and crossbar faults,and can effectively solve the congestion problem in the case of no fault port using the redundant port.The fault tolerance mechanism proposed can tolerate more fault-routers and still maintain good performance in a serious case of congestion.

导出引用

欧阳一鸣, 张一栋, 梁华国, 黄正峰. 三维片上网络故障及拥塞感知的容错路由器设计[J]. 电子学报, 2013, 41(5): 912-917. https://doi.org/10.3969/j.issn.0372-2112.2013.05.013

OUYANG Yi-ming, ZHANG Yi-dong, LIANG Hua-guo, HUANG Zheng-feng. A Fault-Tolerant Design of Faults and Congestion-Aware Router in Three-Dimensional Network-on-Chip[J]. Acta Electronica Sinica, 2013, 41(5): 912-917. https://doi.org/10.3969/j.issn.0372-2112.2013.05.013

中图分类号： TP302

参考文献

[1] B S Feero,P P Pande.Networks-on-chip in a three-dimensional environment:A performance evaluation[J].IEEE Transactions on Computers,2009,58(1):32-45.

[2] 梁华国,李鑫,等.并行折叠计数器的BIST方案[J].电子学报,2012,40(5):1030-1033. Lian Hua-guo,Li Xin,et al.Bist scheme of parallel folding counters[J].Acta Electronica Sinica,2012,40(5):1030-1033.(in Chinese)

[3] J D Owens.Research challenges for on-chip interconnection networks[J].Micro,2007,27(5):96-108.

[4] D Fick,D A Andrew,et al.Vicis:a reliable network for unreliable silicon .Proceedings of Design Automation Conference 2009 .San Francisco:ACM,2009.812-817.

[5] 欧阳一鸣,成丽丽,梁华国.一种基于变长数据块相关性统计的测试数据压缩和解压方法[J].电子学报,2008,36(12):298-302. Ouyang Yi-ming,Cheng Li-li,Lian Hua-guo.A new test data compression technique based on static relativity of variable length data block[J].Acta Electronica Sinica,2008,36(12):298-303.(in Chinese)

[6] 王颀,单智阳,等.串扰约束下超深亚微米顶层互连线性能的优化设计[J].电子学报,2006,34(2):214-219. Wang Qi,Shan Zhi-yang,et al.The optimal design of ultra deep sub-micron global interconnect under crosstalk constraint[J].Acta Electronica Sinica,2006,34(2):214-219.(in Chinese)

[7] G Cristian,P Pande,et al.Methodologices and algorithms for testing switch-based NoC interconnects .Proceedings of International Symposium on Defect and Fault Tolerance in VLSI System .Monterey:IEEE,2005.238-246.

[8] Chao-chao Feng,Zhong-hai Lu,et al.A low-overhead fault-aware deflection routing algorithm for 3D NoC .Proceedings of IEEE Computer Society Annual Symposium .Chennai:IEEE,2011.19-24.

[9] N Rameshan,V Laxmi,et al.Minimal path,fault tolerant,QoS aware routing with node and link failure in 2-D mesh NoC .Proceesings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems .Kyoto:IEEE,2010.60-66.

[10] A DeOrio,D Fick,et al.A reliable routing architecture and algorithm for NoCs .IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2012.31(5):726-739.

[11] K Latif,et al.A novel topology-independent router architecture to enhance reliability and performance of networks-on-Chip .Proceesings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems .Vancouver:IEEE,2011.454-462.