本文提出了一个考虑衬底耦合效应的门延迟模型.该模型在考虑衬底耦合效应下转换CMOS反相器的延迟为等效电阻和电容(RC)网络延迟.考虑工艺参数扰动和衬底耦合效应对门延时的影响,建立基于工艺扰动的简单开关电容门延迟模型,结合随机配置法和多项式的混沌展开法分析门延时.利用数值计算方法对本模型和分析方法进行验证,结果表明与HSPICE精确模型仿真结果的相对误差小于2%,证明本模型和分析方法的有效性.
Abstract
This paper proposes an inverter gate delay model that is comprehensive for inverter gate delay analysis considering substrate coupling.The proposed model transforms the CMOS inverter delay to resistor and capacitance (RC) delay,and then computes the RC network delay under the process variation considering substrate coupling effect.The delay model analysis uses stochastic collocation methods combined with a polynomial chaos,which considers within-die process variation and substrate coupling effect.Experimental results are based on numerical calculation method.Simulation results show that the method’s proportional error is less than 2% compared to HSPICE simulation.
关键词
工艺变化 /
反相器门延时模型 /
衬底耦合效应 /
多项式混沌
{{custom_keyword}} /
Key words
process variation /
inverter gate delay model /
substrate coupling effect /
polynomial chaos theory
{{custom_keyword}} /
中图分类号:
TP211
TN402
{{custom_clc.code}}
({{custom_clc.text}})
{{custom_sec.title}}
{{custom_sec.title}}
{{custom_sec.content}}
参考文献
[1] Chang H,Sapatnekar S S.Statistical Timing analysis under spatial correlations [J].IEEE Transactions on Computer Aided Design,2005,24(9):1467-1482.
[2] Visweswariah C,Ravindra K,et al.First-order Incremental block-based statistical timing analysis [A].ACM/EDAC/IEEE Design Automation Conference [C].Massachusetts:MIT Press,2004.331-336.
[3] Le J,Li X,Pileggi L T.STAC:Statistical Timing analysis with correlation [A].ACM/EDAC/IEEE Design Automation Conference [C].Massachusetts:MIT Press,2005.343-348.
[4] Rabaey J M,Chandrakasan A,Nikolic B.Digital Integrated Circuits [M].Upper Saddle River:Pearson Education,1996.
[5] Shinkai K,Hashimoto M,et al.A gate delay model focusing on current fluctuation over wide-range of process and environmental variability [A].Proc ICCAD [C].Massachusetts:MIT Press,2006.47-53.
[6] Aoki M,Hasegawa K,Itayama K,et al.Variability Analysis of inverter delay time.IEEJ Transactions on Electrical and Electronic Engineering,2010,31(5):646-650.
[7] Charbon E,Gharpure R,et al.Substrate Noise[M].Norwell,MA:Kluwer,2001.
[8] Gray P R,Meyer R G.Analysis and Design of Analog Integrated Circuits[M].New York:Wiley,1984.
[9] Chen P,Kirkpatrick D A,Keutzer K.Static Crosstalk-Noise Analysis[M].New York:Kluwer Academic Publisher,2004.
[10] Predictive Technology Model [OL].http://ptm.asu.edu,2013.
[11] Papoulis A.Probability,Random Variables and Stochastic Process[M].New York:McGraw Hill,1991.
[12] Liu P,Pileggi L T,Strojwas A J.Model order reduction or RC interconnect including variational analysis [A].Design Automation Conferenc [C].Massachusetts:MIT Press,1999.201-206.
[13] Mehrotra V,Sam S,et al.A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance [A].Design Automation Conference [C].Massachusetts:MIT Press,2000.172-175.
[14] Li X,Janet M,et al.Stochastic Analysis of interconnect delay in presence of process variations [J].Journal of Semiconductors,2008,29(2):304-309.
[15] Junmou Z,Eby G F.Decoupling Technique and crosstalk analysis for coupled RLC interconnects [A].Proceeding ISCAS [C].Massachusetts:MIT Press,2004.521-524.
[16] Ghanta P,Vrudhula S,et al.Stochastic power grid analysis considering process variations [A].IEEE Design,Automation,and Test [C].Massachusetts:MIT Press,2005.21-25.
[17] Nassif S R.Modeling and Forecasting of manufacturing variations [A].IEEE Custom Integrated Circuit Conference [C].Massachusetts:MIT Press,2001.223-226.
{{custom_fnGroup.title_cn}}
脚注
{{custom_fn.content}}