电子学报 ›› 2013, Vol. 41 ›› Issue (11): 2256-2261.DOI: 10.3969/j.issn.0372-2112.2013.11.023

• 学术论文 • 上一篇    下一篇

快速设计高性能有符号乘法器电路的编程语言研究

焦继业1, 穆荣2, 郝跃1   

  1. 1. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室, 陕西西安 710071;
    2. 西安科技大学网络中心, 陕西西安 710054
  • 收稿日期:2012-11-30 修回日期:2013-04-08 出版日期:2013-11-25 发布日期:2013-11-25
  • 作者简介:焦继业 男,1977年9月生于新疆乌鲁木齐.西安电子科技大学微电子学院博士研究生,主要从事低功耗高性能计算单元设计、移动三维图形处理器设计和应用、数模混合电路设计等方面的研究工作. E-mail:jiaojiye@126.com 穆 荣 女,1979年10月生于陕西西安.现为西安科技大学网络中心工程师.主要从事移动三维图形处理器设计和应用.嵌入式系统设计等方面的研究工作.
  • 基金资助:
    陕西省自然科学基金(No.2009JM8004)

A Programming Language for Rapid Design of High Performance Signed Multiplier Circuits

JIAO Ji-ye1, MU Rong2, HAO Yue1   

  1. 1. Key Laboratory of Ministry of Education for Wide Band Gap Semiconductor Materials and Devices, Xidian University, Xi'an, Shaanxi 710071, China;
    2. Network Center, Xi'an University of Science and Technology, Xi'an, Shaanxi 710054, China
  • Received:2012-11-30 Revised:2013-04-08 Online:2013-11-25 Published:2013-11-25

摘要: 提出了一种有符号乘法器电路的编程语言,其核心思想是采用指令表示乘法器的编码器、加法器树、快速加法器等三个部分,然后经由指令描述互联关系形成乘法器.通过Lex/Yacc构成编译器,解析程序得到乘法器的Verilog代码.采用该设计语言生成的七种典型结构的32位有符号单周期乘法器,在200MHz工作频率设定下,使用GRACE 0.18μm 1P6M工艺,进行逻辑综合、布局布线、静态时序和功耗分析.实验结果表明,这七种乘法器速度都优于Synopsys Design Ware产生的乘法器,其中由改进型Booth Radix4编码、冗余二进制加法器树和跳跃进位加法器构成的乘法器综合性能超出Synopsys Design Ware产生的乘法器达35%,因此该设计语言可应用于高性能乘法器电路快速设计应用中.

关键词: 乘法器, 编程语言, 编码, 加法器树, 快速加法器

Abstract: This paper presents a programming language for designing signed multiplier circuit.The key idea is using instruction to express the encoding units,addition tree units and fast adder units of multiplier,and using the connection of instruction description to obtain a multiplier.The multiplier of program through Lex and Yacc translate source code containing connection into Verilog code.Seven typical structures of 32 bits signed multipliers are obtained by the instruction description.Under 200MHz synthesis condition and in GRACE 0.18μm process,these multipliers are run for logic synthesis,placed and routed,static timing analysis,and power analysis.The experiment results suggest that the speeds of all the seven multipliers show advantage over that produced by Synopsys design ware,and the multiplier performance composed of modified Booth Radix4 encoding,redundant binary addition tree and carry skip adder exceeds that produced by Synopsys design ware by 35%.Therefore,this language can be used to the application of high performance multiplier design.

Key words: multiplier, programming language, encoding, addition tree, fast adder

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