关键词: 乘法器, 编程语言, 编码, 加法器树, 快速加法器

Abstract: This paper presents a programming language for designing signed multiplier circuit.The key idea is using instruction to express the encoding units,addition tree units and fast adder units of multiplier,and using the connection of instruction description to obtain a multiplier.The multiplier of program through Lex and Yacc translate source code containing connection into Verilog code.Seven typical structures of 32 bits signed multipliers are obtained by the instruction description.Under 200MHz synthesis condition and in GRACE 0.18μm process,these multipliers are run for logic synthesis,placed and routed,static timing analysis,and power analysis.The experiment results suggest that the speeds of all the seven multipliers show advantage over that produced by Synopsys design ware,and the multiplier performance composed of modified Booth Radix4 encoding,redundant binary addition tree and carry skip adder exceeds that produced by Synopsys design ware by 35%.Therefore,this language can be used to the application of high performance multiplier design.

Key words: multiplier, programming language, encoding, addition tree, fast adder