基于多因子CSE算法的AES S-盒电路优化设计

doi:10.3969/j.issn.0372-2112.2014.06.032

电子学报 ›› 2014, Vol. 42 ›› Issue (6): 1238-1243.DOI: 10.3969/j.issn.0372-2112.2014.06.032

基于多因子CSE算法的AES S-盒电路优化设计

曾纯, 吴宁, 张肖强, 周芳, 叶云飞

南京航空航天大学电子信息工程学院, 江苏南京 210016

收稿日期:2013-02-18 修回日期:2013-07-23 出版日期:2014-06-25
- 通讯作者:
- 吴宁
- 作者简介:
- 曾纯女,1989年3月出生于湖南省湘潭县,南京航空航天大学电子信息工程学院硕士生.主要研究方向专用集成电路设计.E-mail：daisyzeng0407201@126.com
- 基金资助:
- 国家自然科学基金资助项目 (No.61376025，No.61106018）; 江苏省产学研前瞻性联合研究项目 (No.BY2013003-11）

The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm

ZENG Chun, WU Ning, ZHANG Xiao-qiang, ZHOU Fang, YE Yun-fei

College of Electrical and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu 210016, China

Received:2013-02-18 Revised:2013-07-23 Online:2014-06-25 Published:2014-06-25

摘要/Abstract

摘要：

针对高级加密标准（AES）S-盒优化，提出了一种新的多因子公共项消除（CSE）优化算法.多因子CSE算法通过对组合逻辑表达式中所含因子最多的公共项优先消除，以简化逻辑表达式，从而有效地减少S-盒电路结构中的GF（2^4）域乘法逆电路和映射矩阵电路的面积和时延.结果表明，多因子CSE算法具有计算速度快，优化效率高的特点.优化后的S-盒组合逻辑电路采用0.18μm CMOS工艺，设计出的S-盒面积-延时积比目前最小面积和最短延时的S-盒组合逻辑电路分别减少了10.32%和19.64%.

关键词: AES, S-盒, 多因子CSE算法

Abstract:

Aiming at the optimization of advanced encryption standard (AES) S-box,a novel multiple-term common subexpression elimination (CSE) algorithm was proposed.In order to simplify the combinational logic expressions,the common subexpressions containing the most factors took priority to be eliminated in the proposed approach,thus effectively reduced the area and latency of the GF(2^4) multiplicative inverse circuit and the isomorphic mapping circuit in S-box.The results show that the multiple-term CSE algorithm achieves high computation and optimization efficiency.The optimized S-box is implemented in 0.18μm CMOS technology.Compared with the smallest S-box and the shortest delay S-box in the existing work,the optimized S-box saves about 10.32% and 19.64% of the area-delay product separately.

Key words: advanced encryption standard (AES), S-box, multiple-term common subexpression elimination (CSE) algorithm

中图分类号:

TN918.4

曾纯, 吴宁, 张肖强, 周芳, 叶云飞. 基于多因子CSE算法的AES S-盒电路优化设计[J]. 电子学报, 2014, 42(6): 1238-1243.

ZENG Chun, WU Ning, ZHANG Xiao-qiang, ZHOU Fang, YE Yun-fei. The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm[J]. Acta Electronica Sinica, 2014, 42(6): 1238-1243.

参考文献

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基于多因子CSE算法的AES S-盒电路优化设计

The Optimization Circuit Design of AES S-Box Based on a Multiple-Term Common Subexpression Elimination Algorithm

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