12.5Gb/s 0.18μmCMOS时钟与数据恢复电路设计

doi:10.3969/j.issn.0372-2112.2014.08.027

电子学报 ›› 2014, Vol. 42 ›› Issue (8): 1630-1635.DOI: 10.3969/j.issn.0372-2112.2014.08.027

12.5Gb/s 0.18μmCMOS时钟与数据恢复电路设计

潘敏^1,2, 冯军¹, 杨婧¹, 杨林成¹

1. 东南大学射频与光电集成电路研究所, 江苏南京 210096;
2. 合肥工业大学计算机与信息学院, 安徽合肥 230001

收稿日期:2013-06-21 修回日期:2013-10-23 出版日期:2014-08-25
- 通讯作者:
- 冯军
- 作者简介:
- 潘敏女，1983年10月出生，安徽桐城人，东南大学在职博士生研究生，合肥工业大学计算机与信息学院教师，研究方向为光纤通信高速集成电路设计.E-mail：panmin@seu.edu.cn
- 基金资助:
- 国家863高技术研究发展计划 (No.2011AA10305）

Design of 12.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

PAN Min^1,2, FENG Jun¹, YANG Jing¹, YANG Lin-cheng¹

1. Institute of RF & OE-ICs, Southeast University, Nanjing, Jiangsu 210096, China;
2. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230001, China

Received:2013-06-21 Revised:2013-10-23 Online:2014-08-25 Published:2014-08-25

摘要/Abstract

摘要：

采用0.18μm CMOS工艺设计实现了一个12.5 Gb/s半速率时钟数据恢复电路（CDR）以及1：2分接器，该CDR及分接器是串行器/解串器（SerDes）接收机中的关键模块，为接收机系统提供6.25GHz的时钟及经二分接后速率降半的6.25Gb/s数据.该电路包括Bang-bang型鉴频鉴相器（PFD）、四级环形压控振荡器（VCO）、V/I转换器、低通滤波器（LPF）、1：2分接器等模块，其中PFD采用一种新型半速率的数据采样时钟型结构，能提高工作速率达到12.5Gb/s.芯片测试结果显示，在1.8V的工作电压下，VCO中心频率在6.25GHz时，调谐范围约为1GHz；输入12Gb/s、长度为2³¹-1的伪随机数据时，得到6GHz时钟的峰峰抖动为9.12ps，均方根（RMS）抖动为1.9ps；整个系统工作性能良好，二分接器输出数据眼图清晰，电路核心模块功耗为150mW，整体芯片面积0.476·0.538mm².

关键词: 串行器/解串器（SerDes）, 时钟数据恢复电路（CDR）, 鉴频鉴相器（PFD）, 压控振荡器（VCO）

Abstract:

12.5 Gb/s half-rate clock and data recovery (CDR) circuit and 1:2 demultiplexer(DEMUX) applied to a serializer/deserializer (SerDes) receiver were designed and implemented in 0.18μm CMOS process.The CDR and DEMUX provided 6.25 GHz clock and 6.25 Gb/s data for the SerDes receiver.The circuit incorporated a Bang-bang phase/frequency detector (PFD),a four-stage ring voltage-controlled oscillator (VCO),a V/I (Voltage-to-Current) converter,a low pass filter (LPF),a 1:2 DEMUX and so on.A new half-rate PFD which sampled the clock by data was adopted,and this PFD could increase operating rate up to 12.5 Gb/s.The tested results show that at the supply voltage of 1.8V,the tune range of VCO is about 1GHz at 6.25GHz centre frequency.When the data rate of the input pseudorandom is 12Gb/s and sequence length is 2³¹-1,the recovered 6GHz clock has a root mean square (RMS) jitter of 1.9ps and a peak-to-peak jitter of 9.12ps.At the same time,the total chip can work well and the eye diagram of output data is clear.The die size is 0.476·0.538 mm² and the core power consumption is only 150mW excluding the output buffers.

Key words: serializer/deserializer (SerDes), clock and data recovery (CDR), ase/frequency detector (PFD), voltage-controlled oscillator (VCO)

中图分类号:

TN913

潘敏, 冯军, 杨婧, 杨林成. 12.5Gb/s 0.18μmCMOS时钟与数据恢复电路设计[J]. 电子学报, 2014, 42(8): 1630-1635.

PAN Min, FENG Jun, YANG Jing, YANG Lin-cheng. Design of 12.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Acta Electronica Sinica, 2014, 42(8): 1630-1635.

参考文献

[1] Zhang Xiaowei,Hu Qingsheng.A 6.25Gbps CMOS 10B/8B decoder with pipelined architecture[J].Journal of semiconductors,2011,32(4):045009-1-4.
[2] Zhao Wenhu,Wang Zhigong.A CMOS word alignment configurable transceiver for multi-standard fiber communication systems[J].Chinese Journal of Electronics,2008,17(2):386-388.
[3] Jayesh Patil,Lili He,Morris Jones.Clock and data recovery for a 6 Gbps SerDes receiver[A].Conference on Computer Science and Information Technology[C].Chengdu:IEEE,2010.217-221.
[4] Sally Safwat,Ezz El-Din Hussein,Maged Ghoneima,et al.A 12Gbps all digital low power SerDes transceiver for on-chip networking circuits and systems[A].International Symposium on Circuits and Systems[C].Rio de Janeiro:IEEE,2011.1419-1422.
[5] Mike Harwood,Steffen Nielsen,Andre Szczepanek,et al.A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications[A].2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers[C].San Francisco:IEEE,2012.326-327.
[6] Jri Lee,Behzad Razavi.A 40-Gb/s clock and data recovery circuit in 0.18μm CMOS technology[J].IEEE Journal of Solid-State Circuits,2003,38(12):2181-2190.
[7] Young-Ho Kwak,Yongtae Kim,Sewook Hwang,et al.A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65nm CMOS process[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2013,60(2):303-313.
[8] Arash Zargaran-Yazd,Shahriar Mirabbasi.12.5-Gb/s full-rate CDR with wideband quadrature phase shifting in data path[J].IEEE Transactions on Circuits and Systems II:Express Briefs,2013,60(6):297-301.
[9] Ansgar Pottbäcker,Ulrich Langmann,Hans-Ulrich Schreiber.A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s[J].IEEE Journal of Solid-State Circuits,1992,27(12):1747-1751.
[10] Zhou Mingzhu,Sun Lingling,Wang Guangyi,et al.Designing 3.125GHz bang-bang PLL for clock recovery in 6.25 Gbps backplane communication receiver[A].2010 International Conference on Microwave and Millimeter Wave Technology[C].Chengdu:IEEE,2010.639-942.
[11] Jafar Savoj,Behzad Razavi.A 10-Gb/s CMOS clock and data recovery circuit with a half-rate Binary phase/frequency detector[J].IEEE Journal of Solid-State Circuits,2003,38(1):13-21.
[12] Yung Sern Tan,Kiat Seng Yeo,Chirn Chye Boon,et al.A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase fetector[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2012,59(6):1156-1167.
[13] 王勇，姚宏颖，王子宇.基于锁相环的10.709 Gbit/s时钟数据再生模块[J].电子学报，2005,33(8):1509-1511. Wang Yong,Yao Hong-ying,Wang Zi-yu.10.709 Gbit/s CDR based on phase locked loop[J].Acta Electronica Sinica,2005,33(8):1509-1511.(in Chinese)
[14] Chang-Lin Hsieh,Hong-Lin Chu,Shen-Iuan Liu.A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13μm CMOS[A].IEEE Asian Solid-State Circuits Conference[C].Taipei：IEEE,2009.165-168
[15] Behzad Razavi 著.光纤通信集成电路设计[M].胡先志，胡佳妮译，北京:人民邮电出版社.2008.210-218.
[16] Wang Junfeng,Feng Jun,Li Yihui,et al.11.6-GHz 0.18μm monolithic CMOS phase-locked loop[J].Journal of Southeast University (English Edition),2007,23(1):35-38.
[17] 潘敏,冯军.低功耗0.18μm 10Gbit/s CMOS 1:4分接器设计[J].东南大学学报(自然科学版),2013,43(2):274-278. Pan Min,Feng Jun.Design of low-power 10Gbit/s 1:4 demultiplexer in 0.18μm CMOS[J].Journal of Southeast University (Natural Science Edition),2013,43(2):274-278.(in Chinese)

12.5Gb/s 0.18μmCMOS时钟与数据恢复电路设计

Design of 12.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

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