电子学报 ›› 2014, Vol. 42 ›› Issue (11): 2310-2313.DOI: 10.3969/j.issn.0372-2112.2014.11.028

• 科研通信 • 上一篇    下一篇

并发追踪数据流的多缓存选址算法

高建良, 李欣, 王建新   

  1. 中南大学信息科学与工程学院, 湖南长沙 410083
  • 收稿日期:2014-01-10 修回日期:2014-06-05 出版日期:2014-11-25
    • 通讯作者:
    • 王建新
    • 作者简介:
    • 高建良 男,1979年出生于湖南省,博士,副教授,硕士生导师.主要研究方向为计算机系统结构、大规模数据处理等. E-mail:gjlpaper@gmail.com;李欣 男,1988年出生于安徽省蚌埠市,硕士.主要研究方向为多核芯片调试技术. E-mail:leexin47@163.com
    • 基金资助:
    • 国家自然科学基金 (No.61106036)

Multi-Buffer Location Selection Algorithm for Concurrent Trace Data Flows

GAO Jian-liang, LI Xin, WANG Jian-xin   

  1. School of Information Science and Engineering, Central South University, Changsha, Hunan 410083, China
  • Received:2014-01-10 Revised:2014-06-05 Online:2014-11-25 Published:2014-11-25
    • Supported by:
    • National Natural Science Foundation of China (No.61106036)

摘要:

为了验证多核芯片的正确性,通常需要同时观测不同芯核上的多组信号.如何实时处理并发追踪中多组数据流已经成为多核芯片硅后功能验证所面临的关键挑战之一.本文提出了一种基于映射的自调节缓存选址(Map-Based Self-Regulation Location Selection,MSLS)算法,该算法通过优化多缓存选址,在片上网络通信带宽限制下保证了并发追踪数据流能够实时存储,同时降低了追踪数据流传输能耗.实验结果表明了该方法的有效性.

关键词: 多核芯片, 硅后调试, 并发追踪, 多缓存选址, 片上网络

Abstract:

With the development of multi-core processors,it becomes a key problem to transmit concurrent trace data simultaneously to on-chip buffer under bandwidth constraint.To deal with the problem,we propose a Map-based Self-regulation Location Selection (MSLS) algorithm.This algorithm locates multiple trace buffers in interconnection fabrics under the bandwidth constraint,and reduces the average distance between trace sources and trace buffers.Experimental results show our algorithm can achieve high efficiency for post-silicon debug.

Key words: multi-core chip, post-silicon debug, concurrent trace, multi-buffer location selection, network-on-chip

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