[1] Businger P A,Golub G H.Algorithm 358:singular value decomposition of a complex matrix[F1,4,5][J].Communications of the ACM,1969,12(10):564-565.
[2] Demmel J,Kahan W.Accurate singular values of bidiagonal matrices[J].SIAM Journal on Scientific and Statistical Computing,1990,11(5):873-912.
[3] Forsythe G E,Henrici P.The cyclic Jacobi method for computing the principal values of a complex matrix[J].Transactions of the American Mathematical Society,1960,94(1):1-23.
[4] Cavallaro J R,et al.VLSI implementation of a CORDIC SVD processor[A].University Government Industry Microelectronics Symposium[C].IEEE,1989.256-260.
[5] Ma W,et al.An FPGA-based singular value decomposition processor[A].Canadian Conference on Electrical and Computer Engineering[C].Ottawa:IEEE,2006.1047-1050.
[6] Szecówka P M,Malinowski P.CORDIC and SVD implementation in digital hardware[A].Mixed Design of Integrated Circuits and Systems[C].Wroclaw:IEEE,2010.237-242.
[7] Brent R P,et al.The solution of singular-value and symmetric eigenvalue problems on multiprocessor arrays[J].SIAM Journal on Scientific and Statistical Computing,1985,6(1):69-84.
[8] 谭曼琼,等.位串行SVD处理器的设计[J].小型微型计算机系统,2012,33(006):1358-1362. Tan Man-qiong,et al.Design of bit-serial singular value decomposition processor[J].2012,33(006):1358-1362.(in Chinese)
[9] Huang Kuan-Ju.A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis[A].Engineering in Medicine and Biology Society[C].Osaka:IEEE,2013.1944-1947.
[10] 陈刚,等.基于CORDIC算法的高精度浮点对称矩阵特征值分解的FPGA实现[J].计算机科学,2013,40(5):35-37. Chen Gang,et al.Floating-point CORDIC-based real-valued symmetric matrix eigenvalue decomposition on FPGA[J].Computer Science,2013,40(5):35-37.(in Chinese)
[11] 毕卓,戴益君.全定制CORDIC运算器设计[J].计算机工程与科学,2011,33(10):64-69. Bi Zhuo,Dai Yi-jun.Full custom CORDIC arithmetic unit design[J].Computer Engineering and Science,2011,33(10):64-69.(in Chinese)
[12] J E Volder.The CORDIC trigonometric computing technique[J].IRE Transactions on Electronic Computers,1959,8(33):330-334.
[13] E Antelo,J Villalba,E L Zapata.A low-latency pipelined 2D and 3D CORDIC processors[J].IEEE Transactions on Computers,2008,57(3):404-417.
[14] Ahmedsaid A,Amira A,Bouridane A.Improved SVD systolic array and implementation on FPGA[A].Field-Programmable Technology[C].Tokyo:IEEE,2003.35-42.