魂芯DSP的编译器设计与优化

doi:10.3969/j.issn.0372-2112.2015.08.028

电子学报 ›› 2015, Vol. 43 ›› Issue (8): 1656-1661.DOI: 10.3969/j.issn.0372-2112.2015.08.028

魂芯DSP的编译器设计与优化

王向前¹, 洪一^1,2, 王昊², 郑启龙³

1. 合肥工业大学计算机与信息学院, 安徽合肥 230009;
2. 中国电子科技集团公司第三十八研究所, 安徽合肥 230088;
3. 中国科学技术大学计算机科学与技术学院, 安徽合肥 230027

收稿日期:2014-03-25 修回日期:2014-07-28 出版日期:2015-08-25
- 作者简介:
- 王向前 男,1985年生,河南南阳人,合肥工业大学博士研究生.从事的主要研究方向为编译优化与系统软件优化. E-mail:forward@mail.ustc.edu.cn 洪一 男,1963年生,安徽铜陵人,合肥工业大学教授、博士生导师、中国电科首席专家、"魂芯"DSP总设计师.主要研究方向为信号处理与信号处理器体系结构设计. 王昊 男,1977年生,吉林松原人,中国电科第三十八所工程师.从事的主要研究工作为编译设计与优化. 郑启龙 男,1969年生,安徽合肥人,中国科学技术大学副教授.主要研究方向为并行计算与高效能软件工具与环境.
- 基金资助:
- 国家核高基重大专项 (No.2012ZX01034001-001)

Compiler Design and Optimization for BWDSP

WANG Xiang-qian¹, HONG Yi^1,2, WANG Hao², ZHENG Qi-long³

1. School of Computer and Information, Hefei University of Technology, Hefei, Anhui 230009, China;
2. No.38 Research Institute, China Electronics Technology Group Corporation, Hefei, Anhui 230088, China;
3. School of Computer Science and Technology, University of Science and Technology of China, Hefei, Anhui 230027, China

Received:2014-03-25 Revised:2014-07-28 Online:2015-08-25 Published:2015-08-25
- Supported by:
- National Science and Technology Major Project (NSTMP) Program Kernal Electronic Devices, High-end General Application Chips, Fundamental Software Products (No.2012ZX01034001-001)

摘要/Abstract

摘要：

魂芯DSP是一款字寻址的、分簇结构的、支持SIMD的VLIW处理器.介绍了基于开源编译器基础设施open64开发魂芯编译器的关键技术,包括地址寄存器的优化处理、综合多种启发因子的指令分簇、分簇架构下的寄存器分配和指令调度.介绍了魂芯DSP编译器的体系结构优化关键技术,包括基于依赖分析的向量化、高效指令的使用和零开销循环的识别.并总结开发经验,给出了基于开源编译基础设施开发编译器的若干注意点.

关键词: 地址寄存器, 分簇, 向量化, 零开销循环

Abstract:

BWDSP is a word addressed VLIW DSP supporting clustering and SIMD.Based on open source compiling infrastructure open64, key technologies of compiler are developed for BWDSP which consist of optimized processing of address register, instruction clustering combined multi-heuristic factors, register allocation and instruction scheduling on clustering architecture.The key optimization technologies of BWDSP compiler on its hardware architecture include vectorization based on dependence analysis, application of effective instruction and recognization of zero overhead loop.Some general attention points for compiler development based on open source compiler infrastructure are presented after the development experience on BWDSP compiler is summarized.

Key words: address register, clustering, vectorization, zero overhead loop

中图分类号:

TP314

王向前, 洪一, 王昊, 等. 魂芯DSP的编译器设计与优化[J]. 电子学报, 2015, 43(8): 1656-1661.

WANG Xiang-qian, HONG Yi, WANG Hao, et al. Compiler Design and Optimization for BWDSP[J]. Acta Electronica Sinica, 2015, 43(8): 1656-1661.

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魂芯DSP的编译器设计与优化

Compiler Design and Optimization for BWDSP

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