一种基于电压窗口技术的超低功耗SAR ADC

doi:10.3969/j.issn.0372-2112.2016.01.031

电子学报 ›› 2016, Vol. 44 ›› Issue (1): 211-215.DOI: 10.3969/j.issn.0372-2112.2016.01.031

一种基于电压窗口技术的超低功耗SAR ADC

汪正锋, 宁宁, 吴霜毅, 杜翎, 蒋旻, 闫小艳, 王伟

电子科技大学电子薄膜与集成器件国家重点实验室, 四川成都 610054

收稿日期:2014-06-19 修回日期:2014-09-24 出版日期:2016-01-25
- 通讯作者:
- 宁宁
- 作者简介:
- 汪正锋 男,1990年06月出生,湖北黄梅人.2012年毕业于重庆邮电大学光电工程学院微电子学专业,2012年起于电子科技大学微电子与固体电子学院微电子与固体电子学专业就读研究生,主要从事数模混合集成电路设计. E-mail:wangzhf0832@163.com
- 基金资助:
- 国家自然科学基金 (No.61404022); 中央高校基本科研业务费 (No.ZYGX2012Z007)

An Ultra-Low Power SAR ADC with Voltage Window Technique

WANG Zheng-feng, NING Ning, WU Shuang-yi, DU Ling, JIANG Min, YAN Xiao-yan, WANG Wei

State Key Lab of Electronic Thin Film and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, Sichuan 610054, China

Received:2014-06-19 Revised:2014-09-24 Online:2016-01-25 Published:2016-01-25

摘要/Abstract

摘要：

本文提出了一种应用于生物医学的超低功耗逐次逼近型模数转换器(SAR ADC).针对SAR ADC主要模块进行超低功耗设计.数模转换(DAC)电路采用vcm-based以及分段电容阵列结构来减小其总电容,从而降低了DAC功耗.同时提出了电压窗口的方法在不降低比较器精度的情况下减小其功耗.此外,采用堆栈以及多阈值晶体管结构来减小低频下的漏电流.在55nm工艺下进行设计和仿真,在0.6V电源电压以及10kS/s的采样频率下,ADC的信噪失真比(SNDR)为73.3dB,总功耗为432nW,品质因数(FOM)为11.4fJ/Conv.

关键词: 模数转换器(ADC), 逐次逼近寄存器(SAR), 电压窗口, 超低功耗

Abstract:

An ultra-low power successive approximation register analog-to-digital converter for biomedical application is proposed.Many ultra-low power design methods are utilized for its main modules.The digital-to-analog converter (DAC) employs a vcm-based and split capacitor array structure to cut down the total capacitance, so as the power consumption.Voltage window technique is used to decrease the power consumption of the comparator without sacrificing its accuracy.Furthermore, stack forcing and multi-Vt design approaches are used to reduce the leakage current under low frequency.The proposed SAR ADC is designed and simulated in 55nm process.With 0.6V power supply and 10kS/s sampling rate, the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 73.3dB.The total power consumption is 432nW and the figure-of-merit (FOM) is 11.4fJ/Conv.

Key words: analog-to-digital converter (ADC), successive approximation register (SAR), voltage window, ultra-low power

中图分类号:

TN402

汪正锋, 宁宁, 吴霜毅, 杜翎, 蒋旻, 闫小艳, 王伟. 一种基于电压窗口技术的超低功耗SAR ADC[J]. 电子学报, 2016, 44(1): 211-215.

WANG Zheng-feng, NING Ning, WU Shuang-yi, DU Ling, JIANG Min, YAN Xiao-yan, WANG Wei. An Ultra-Low Power SAR ADC with Voltage Window Technique[J]. Acta Electronica Sinica, 2016, 44(1): 211-215.

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一种基于电压窗口技术的超低功耗SAR ADC

An Ultra-Low Power SAR ADC with Voltage Window Technique

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