[1] Jabbar M H,M'zah A,Hammami O,et al.Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance[A].Masahiro Fujita.Proceedings of the Fifth Asia Symposium on Quality Electronic Design (ASQED)[C].Penang,Malaysia:IEEE,2013.249-255.
[2] Hammami O,Hamwi K.MHYNESYS Ⅱ:multi-stage hybrid network on chip synthesis for next generation 3D IC manycore[A].Chang Wen Chen.IEEE International Symposium on Circuits and Systems (ISCAS)[C].Beijing:IEEE,2013.325-328.
[3] 虞潇,李丽,张宇昂,等.一种面向功耗免死锁三维全动态3D NoC路由算法[J].电子学报,2013,41(2):329-334. YU Xiao,LI Li,ZHANG Yu-ang,et al.A power-aware sead lock avoid three-dimensional full-adaptive routing algorithm for 3D NoC[J].Acta Electronica Sinica,2013,41(2):329-334.(in Chinese)
[4] Hamedani P K,Hessabi S,Sarbazi-Azad H,et al.Exploration oftemperature constraints for thermal aware mapping of 3D networks on chip[A].Rainer Stotzka.Proceedings of the 20th International Euromicro International Conference on Parallel,Distributed and Network-Based Processing (PDP 2012)[C].Garching,Germany:IEEE Computer Society,2012.499-506.
[5] Rahmani A M,Vaddina K R,Latif K,et al.Design and management of high-performance,reliable and thermal-aware 3D networks-on-chip[J].IET Circuits,Devices & Systems,2012,6(5):308-321.
[6] Wei Huang,Ghosh S,Velusamy S,et al.HotSpot:a compact thermal modeling methodology for early-stage VLSI design[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006,14(5):501-513.
[7] Addo-Quaye C.Thermal-aware mapping and placement for 3-D NoC designs[A].Dong Ha.IEEE International SOC Conference[C].Herdon,Virginia,USA:IEEE,2005.25-28.
[8] 闫佳琪,骆祖莹,唐亮,等.考虑温度对漏电流功耗影响的MPSoC结构级热分析方法[J].计算机辅助设计与图形学学报,2013,25(11):1767-1774. Yan Jia-qi,Luo Zu-yin,Tang Liang,et al.High accurate architecture-leve thermal analysis methods for MPSoCs considering leakage power dependence on temperature[J].Journal of Computer-Aided Design & Computer Graphics,2013,25(11):1767-1774.(in Chinese)
[9] Bartolini A,Cacciari M,Tilli A,et al.Thermal and energy management of high-performance multicores:distributed and self-calibrating model-predictive controller[J].IEEE Transactions on Parallel and Distributed Systems,2013,24(1):170-183.
[10] Shuang Xie,Wai Tung Ng.Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA[A].Piotr Dudek.IEEE International Symposium on Circuits and Systems (ISCAS)[C].Melbourne VIC,Australia:IEEE,2014.2571-2574.
[11] Coskun A K,Rosing T S,Gross K C.Utilizing predictors for efficient thermal management in multiprocessor SoCs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2009,28(10):1503-1516.
[12] Zanini F,Atienza D,De Micheli G.A control theory approach for thermal balancing of MPSoC[A].Kazutoshi Wakabayashi.Proceedings of the 14th Asia and South Pacific Design Automation Conference[C].Yokohama,Japan:IEEE,2009.37-42.
[13] Xiaorui Wang,Kai Ma,Yefu Wang.Adaptive power control with online model estimation for chip multiprocessors[J].IEEE Transactions on Parallel and Distributed Systems,2011,22(10):1681-1696.
[14] Inchoon Yeo,Chih Chun Liu,Eun Jung Kim.Predictive dynamic thermal management for multicore systems[A].Limor Fix.Proceedings of the 45th Design Automation Conference[C].Anaheim,California,USA:ACM,2008.734-739.
[15] Bartolini A,Cacciari M,Tilli A,et al.A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores[A].Kathy Preas.Proceedings of Design,Automation & Test in Europe Conference & Exhibition (DATE)[C].Grenoble,France:EDAA,2011.1-6.
[16] Dacheng Juan,Huapeng Zhou,Marculescu D,et al.A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors[A].Kazutoshi Wakabayashi.Proceedings of the 17th Asia and South Pacific Design Automation Conference[C].Sydney,Australia:IEEE,2012.597-602.
[17] Kun-Chih Chen,Shu-Yen Lin,An-Yeu Wu.Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems[A].Ilderem V.Proceedings of the International Symposium on VLSI Design,Automation,and Test (VLSI-DAT)[C].Hsinchu:IEEE,2013.1-4.
[18] Shengquan Wang,Bettati R.Reactive speed control in temperature-constrained real-time systems[A].Stephanie Kawada.Proceedings of the 18th Euromicro Conference on Real-Time Systems[C].Dresden,Germany:IEEE Computer Society,2006.161-170.
[19] Skadron K,Stan M R,Wei Huang,et al.Temperature-aware microarchitecture[A].Bob Werner.Proceedings of the 30th Annual International Symposium on Computer Architecture[C].San Diego,California,USA:IEEE Computer Society,2003.2-13.
[20] Sungjun Im,Banerjee K.Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs[A].Mark Law.2000 International Electron Devices Meeting[C].San Francisco,California,USA:IEEE,2000.727-730.
[21] Wei Huang,Allen-Ware M,Carter J B,et al.Temperature-aware architecture:lessons and opportunities[J].IEEE Micro,2011,31(3):82-86. |